|
@@ -90,7 +90,6 @@
|
|
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
|
|
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
|
|
#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
|
|
#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
|
|
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
|
|
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
|
|
-#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
|
|
|
|
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
|
|
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
|
|
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
|
|
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
|
|
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
|
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
|
@@ -103,6 +102,7 @@
|
|
#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
|
|
#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
|
|
|
|
|
|
#define AT91SAM9G45_BASE_ECC 0xffffe200
|
|
#define AT91SAM9G45_BASE_ECC 0xffffe200
|
|
|
|
+#define AT91SAM9G45_BASE_DMA 0xffffec00
|
|
#define AT91SAM9G45_BASE_PIOA 0xfffff200
|
|
#define AT91SAM9G45_BASE_PIOA 0xfffff200
|
|
#define AT91SAM9G45_BASE_PIOB 0xfffff400
|
|
#define AT91SAM9G45_BASE_PIOB 0xfffff400
|
|
#define AT91SAM9G45_BASE_PIOC 0xfffff600
|
|
#define AT91SAM9G45_BASE_PIOC 0xfffff600
|