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+/*
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+ * ARC700 VIPT Cache Management
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+ *
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+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs
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+ * -flush_cache_dup_mm (fork)
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+ * -likewise for flush_cache_mm (exit/execve)
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+ * -likewise for flush_cache_range,flush_cache_page (munmap, exit, COW-break)
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+ *
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+ * vineetg: Apr 2011
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+ * -Now that MMU can support larger pg sz (16K), the determiniation of
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+ * aliasing shd not be based on assumption of 8k pg
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+ *
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+ * vineetg: Mar 2011
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+ * -optimised version of flush_icache_range( ) for making I/D coherent
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+ * when vaddr is available (agnostic of num of aliases)
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+ *
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+ * vineetg: Mar 2011
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+ * -Added documentation about I-cache aliasing on ARC700 and the way it
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+ * was handled up until MMU V2.
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+ * -Spotted a three year old bug when killing the 4 aliases, which needs
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+ * bottom 2 bits, so we need to do paddr | {0x00, 0x01, 0x02, 0x03}
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+ * instead of paddr | {0x00, 0x01, 0x10, 0x11}
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+ * (Rajesh you owe me one now)
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+ *
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+ * vineetg: Dec 2010
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+ * -Off-by-one error when computing num_of_lines to flush
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+ * This broke signal handling with bionic which uses synthetic sigret stub
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+ *
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+ * vineetg: Mar 2010
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+ * -GCC can't generate ZOL for core cache flush loops.
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+ * Conv them into iterations based as opposed to while (start < end) types
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+ *
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+ * Vineetg: July 2009
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+ * -In I-cache flush routine we used to chk for aliasing for every line INV.
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+ * Instead now we setup routines per cache geometry and invoke them
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+ * via function pointers.
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+ *
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+ * Vineetg: Jan 2009
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+ * -Cache Line flush routines used to flush an extra line beyond end addr
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+ * because check was while (end >= start) instead of (end > start)
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+ * =Some call sites had to work around by doing -1, -4 etc to end param
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+ * =Some callers didnt care. This was spec bad in case of INV routines
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+ * which would discard valid data (cause of the horrible ext2 bug
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+ * in ARC IDE driver)
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+ *
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+ * vineetg: June 11th 2008: Fixed flush_icache_range( )
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+ * -Since ARC700 caches are not coherent (I$ doesnt snoop D$) both need
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+ * to be flushed, which it was not doing.
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+ * -load_module( ) passes vmalloc addr (Kernel Virtual Addr) to the API,
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+ * however ARC cache maintenance OPs require PHY addr. Thus need to do
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+ * vmalloc_to_phy.
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+ * -Also added optimisation there, that for range > PAGE SIZE we flush the
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+ * entire cache in one shot rather than line by line. For e.g. a module
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+ * with Code sz 600k, old code flushed 600k worth of cache (line-by-line),
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+ * while cache is only 16 or 32k.
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/mm.h>
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+#include <linux/sched.h>
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+#include <linux/cache.h>
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+#include <linux/mmu_context.h>
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+#include <linux/syscalls.h>
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+#include <linux/uaccess.h>
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+#include <asm/cacheflush.h>
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+#include <asm/cachectl.h>
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+#include <asm/setup.h>
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+
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+
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+#ifdef CONFIG_ARC_HAS_ICACHE
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+static void __ic_line_inv_no_alias(unsigned long, int);
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+static void __ic_line_inv_2_alias(unsigned long, int);
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+static void __ic_line_inv_4_alias(unsigned long, int);
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+
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+/* Holds the ptr to flush routine, dependign on size due to aliasing issues */
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+static void (*___flush_icache_rtn) (unsigned long, int);
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+#endif
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+
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+/*
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+ * Read the Cache Build Confuration Registers, Decode them and save into
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+ * the cpuinfo structure for later use.
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+ * No Validation done here, simply read/convert the BCRs
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+ */
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+void __init read_decode_cache_bcr(void)
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+{
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+ struct bcr_cache ibcr, dbcr;
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+ struct cpuinfo_arc_cache *p_ic, *p_dc;
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+ unsigned int cpu = smp_processor_id();
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+
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+ p_ic = &cpuinfo_arc700[cpu].icache;
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+ READ_BCR(ARC_REG_IC_BCR, ibcr);
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+
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+ if (ibcr.config == 0x3)
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+ p_ic->assoc = 2;
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+ p_ic->line_len = 8 << ibcr.line_len;
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+ p_ic->sz = 0x200 << ibcr.sz;
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+ p_ic->ver = ibcr.ver;
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+
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+ p_dc = &cpuinfo_arc700[cpu].dcache;
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+ READ_BCR(ARC_REG_DC_BCR, dbcr);
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+
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+ if (dbcr.config == 0x2)
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+ p_dc->assoc = 4;
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+ p_dc->line_len = 16 << dbcr.line_len;
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+ p_dc->sz = 0x200 << dbcr.sz;
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+ p_dc->ver = dbcr.ver;
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+}
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+
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+/*
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+ * 1. Validate the Cache Geomtery (compile time config matches hardware)
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+ * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn)
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+ * (aliasing D-cache configurations are not supported YET)
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+ * 3. Enable the Caches, setup default flush mode for D-Cache
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+ * 3. Calculate the SHMLBA used by user space
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+ */
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+void __init arc_cache_init(void)
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+{
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+ unsigned int temp;
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+#ifdef CONFIG_ARC_CACHE
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+ unsigned int cpu = smp_processor_id();
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+#endif
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+#ifdef CONFIG_ARC_HAS_ICACHE
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+ struct cpuinfo_arc_cache *ic;
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+#endif
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+#ifdef CONFIG_ARC_HAS_DCACHE
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+ struct cpuinfo_arc_cache *dc;
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+#endif
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+ int way_pg_ratio = way_pg_ratio;
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+
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+#ifdef CONFIG_ARC_HAS_ICACHE
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+ ic = &cpuinfo_arc700[cpu].icache;
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+
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+ /*
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+ * if Cache way size is <= page size then no aliasing exhibited
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+ * otherwise ratio determines num of aliases.
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+ * e.g. 32K I$, 2 way set assoc, 8k pg size
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+ * way-sz = 32k/2 = 16k
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+ * way-pg-ratio = 16k/8k = 2, so 2 aliases possible
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+ * (meaning 1 line could be in 2 possible locations).
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+ */
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+ way_pg_ratio = ic->sz / ARC_ICACHE_WAYS / PAGE_SIZE;
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+ switch (way_pg_ratio) {
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+ case 0:
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+ case 1:
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+ ___flush_icache_rtn = __ic_line_inv_no_alias;
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+ break;
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+ case 2:
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+ ___flush_icache_rtn = __ic_line_inv_2_alias;
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+ break;
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+ case 4:
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+ ___flush_icache_rtn = __ic_line_inv_4_alias;
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+ break;
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+ default:
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+ panic("Unsupported I-Cache Sz\n");
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+ }
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+#endif
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+
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+ /* Enable/disable I-Cache */
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+ temp = read_aux_reg(ARC_REG_IC_CTRL);
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+
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+#ifdef CONFIG_ARC_HAS_ICACHE
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+ temp &= ~IC_CTRL_CACHE_DISABLE;
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+#else
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+ temp |= IC_CTRL_CACHE_DISABLE;
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+#endif
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+
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+ write_aux_reg(ARC_REG_IC_CTRL, temp);
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+
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+#ifdef CONFIG_ARC_HAS_DCACHE
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+ dc = &cpuinfo_arc700[cpu].dcache;
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+
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+ /* check for D-Cache aliasing */
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+ if ((dc->sz / ARC_DCACHE_WAYS) > PAGE_SIZE)
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+ panic("D$ aliasing not handled right now\n");
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+#endif
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+
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+ /* Set the default Invalidate Mode to "simpy discard dirty lines"
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+ * as this is more frequent then flush before invalidate
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+ * Ofcourse we toggle this default behviour when desired
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+ */
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+ temp = read_aux_reg(ARC_REG_DC_CTRL);
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+ temp &= ~DC_CTRL_INV_MODE_FLUSH;
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+
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+#ifdef CONFIG_ARC_HAS_DCACHE
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+ /* Enable D-Cache: Clear Bit 0 */
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+ write_aux_reg(ARC_REG_DC_CTRL, temp & ~IC_CTRL_CACHE_DISABLE);
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+#else
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+ /* Flush D cache */
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+ write_aux_reg(ARC_REG_DC_FLSH, 0x1);
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+ /* Disable D cache */
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+ write_aux_reg(ARC_REG_DC_CTRL, temp | IC_CTRL_CACHE_DISABLE);
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+#endif
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+
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+ return;
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+}
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+
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+#define OP_INV 0x1
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+#define OP_FLUSH 0x2
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+#define OP_FLUSH_N_INV 0x3
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+
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+#ifdef CONFIG_ARC_HAS_DCACHE
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+
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+/***************************************************************
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+ * Machine specific helpers for Entire D-Cache or Per Line ops
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+ */
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+
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+static inline void wait_for_flush(void)
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+{
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+ while (read_aux_reg(ARC_REG_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
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+ ;
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+}
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+
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+/*
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+ * Operation on Entire D-Cache
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+ * @cacheop = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV}
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+ * Note that constant propagation ensures all the checks are gone
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+ * in generated code
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+ */
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+static inline void __dc_entire_op(const int cacheop)
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+{
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+ unsigned long flags, tmp = tmp;
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+ int aux;
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+
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+ local_irq_save(flags);
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+
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+ if (cacheop == OP_FLUSH_N_INV) {
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+ /* Dcache provides 2 cmd: FLUSH or INV
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+ * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
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+ * flush-n-inv is achieved by INV cmd but with IM=1
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+ * Default INV sub-mode is DISCARD, which needs to be toggled
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+ */
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+ tmp = read_aux_reg(ARC_REG_DC_CTRL);
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+ write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH);
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+ }
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+
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+ if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
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+ aux = ARC_REG_DC_IVDC;
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+ else
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+ aux = ARC_REG_DC_FLSH;
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+
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+ write_aux_reg(aux, 0x1);
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+
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+ if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */
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+ wait_for_flush();
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+
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+ /* Switch back the DISCARD ONLY Invalidate mode */
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+ if (cacheop == OP_FLUSH_N_INV)
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+ write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH);
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+
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+ local_irq_restore(flags);
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+}
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+
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+/*
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+ * Per Line Operation on D-Cache
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+ * Doesn't deal with type-of-op/IRQ-disabling/waiting-for-flush-to-complete
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+ * It's sole purpose is to help gcc generate ZOL
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+ */
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+static inline void __dc_line_loop(unsigned long start, unsigned long sz,
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+ int aux_reg)
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+{
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+ int num_lines, slack;
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+
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+ /* Ensure we properly floor/ceil the non-line aligned/sized requests
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+ * and have @start - aligned to cache line and integral @num_lines.
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+ * This however can be avoided for page sized since:
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+ * -@start will be cache-line aligned already (being page aligned)
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+ * -@sz will be integral multiple of line size (being page sized).
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+ */
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+ if (!(__builtin_constant_p(sz) && sz == PAGE_SIZE)) {
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+ slack = start & ~DCACHE_LINE_MASK;
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+ sz += slack;
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+ start -= slack;
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+ }
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+
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+ num_lines = DIV_ROUND_UP(sz, ARC_DCACHE_LINE_LEN);
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+
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+ while (num_lines-- > 0) {
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+#if (CONFIG_ARC_MMU_VER > 2)
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+ /*
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+ * Just as for I$, in MMU v3, D$ ops also require
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+ * "tag" bits in DC_PTAG, "index" bits in FLDL,IVDL ops
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+ * But we pass phy addr for both. This works since Linux
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+ * doesn't support aliasing configs for D$, yet.
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+ * Thus paddr is enough to provide both tag and index.
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+ */
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+ write_aux_reg(ARC_REG_DC_PTAG, start);
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+#endif
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+ write_aux_reg(aux_reg, start);
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+ start += ARC_DCACHE_LINE_LEN;
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+ }
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+}
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+
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+/*
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+ * D-Cache : Per Line INV (discard or wback+discard) or FLUSH (wback)
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+ */
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+static inline void __dc_line_op(unsigned long start, unsigned long sz,
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+ const int cacheop)
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+{
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+ unsigned long flags, tmp = tmp;
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+ int aux;
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+
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+ local_irq_save(flags);
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+
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+ if (cacheop == OP_FLUSH_N_INV) {
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+ /*
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+ * Dcache provides 2 cmd: FLUSH or INV
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+ * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
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+ * flush-n-inv is achieved by INV cmd but with IM=1
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+ * Default INV sub-mode is DISCARD, which needs to be toggled
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+ */
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+ tmp = read_aux_reg(ARC_REG_DC_CTRL);
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+ write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH);
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+ }
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+
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+ if (cacheop & OP_INV) /* Inv / flush-n-inv use same cmd reg */
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+ aux = ARC_REG_DC_IVDL;
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+ else
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+ aux = ARC_REG_DC_FLDL;
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+
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+ __dc_line_loop(start, sz, aux);
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+
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+ if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */
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+ wait_for_flush();
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+
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+ /* Switch back the DISCARD ONLY Invalidate mode */
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+ if (cacheop == OP_FLUSH_N_INV)
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+ write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH);
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+
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+ local_irq_restore(flags);
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+}
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+
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+#else
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+
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+#define __dc_entire_op(cacheop)
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+#define __dc_line_op(start, sz, cacheop)
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+
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+#endif /* CONFIG_ARC_HAS_DCACHE */
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+
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+
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+#ifdef CONFIG_ARC_HAS_ICACHE
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+
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+/*
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+ * I-Cache Aliasing in ARC700 VIPT caches
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+ *
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+ * For fetching code from I$, ARC700 uses vaddr (embedded in program code)
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+ * to "index" into SET of cache-line and paddr from MMU to match the TAG
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+ * in the WAYS of SET.
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+ *
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+ * However the CDU iterface (to flush/inv) lines from software, only takes
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+ * paddr (to have simpler hardware interface). For simpler cases, using paddr
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+ * alone suffices.
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+ * e.g. 2-way-set-assoc, 16K I$ (8k MMU pg sz, 32b cache line size):
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+ * way_sz = cache_sz / num_ways = 16k/2 = 8k
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+ * num_sets = way_sz / line_sz = 8k/32 = 256 => 8 bits
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+ * Ignoring the bottom 5 bits corresp to the off within a 32b cacheline,
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+ * bits req for calc set-index = bits 12:5 (0 based). Since this range fits
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+ * inside the bottom 13 bits of paddr, which are same for vaddr and paddr
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+ * (with 8k pg sz), paddr alone can be safely used by CDU to unambigously
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+ * locate a cache-line.
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+ *
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+ * However for a difft sized cache, say 32k I$, above math yields need
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+ * for 14 bits of vaddr to locate a cache line, which can't be provided by
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+ * paddr, since the bit 13 (0 based) might differ between the two.
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+ *
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+ * This lack of extra bits needed for correct line addressing, defines the
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+ * classical problem of Cache aliasing with VIPT architectures
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+ * num_aliases = 1 << extra_bits
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+ * e.g. 2-way-set-assoc, 32K I$ with 8k MMU pg sz => 2 aliases
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+ * 2-way-set-assoc, 64K I$ with 8k MMU pg sz => 4 aliases
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+ * 2-way-set-assoc, 16K I$ with 8k MMU pg sz => NO aliases
|
|
|
+ *
|
|
|
+ * ------------------
|
|
|
+ * MMU v1/v2 (Fixed Page Size 8k)
|
|
|
+ * ------------------
|
|
|
+ * The solution was to provide CDU with these additonal vaddr bits. These
|
|
|
+ * would be bits [x:13], x would depend on cache-geom.
|
|
|
+ * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
|
|
|
+ * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
|
|
|
+ * orig 5 bits of paddr were anyways ignored by CDU line ops, as they
|
|
|
+ * represent the offset within cache-line. The adv of using this "clumsy"
|
|
|
+ * interface for additional info was no new reg was needed in CDU.
|
|
|
+ *
|
|
|
+ * 17:13 represented the max num of bits passable, actual bits needed were
|
|
|
+ * fewer, based on the num-of-aliases possible.
|
|
|
+ * -for 2 alias possibility, only bit 13 needed (32K cache)
|
|
|
+ * -for 4 alias possibility, bits 14:13 needed (64K cache)
|
|
|
+ *
|
|
|
+ * Since vaddr was not available for all instances of I$ flush req by core
|
|
|
+ * kernel, the only safe way (non-optimal though) was to kill all possible
|
|
|
+ * lines which could represent an alias (even if they didnt represent one
|
|
|
+ * in execution).
|
|
|
+ * e.g. for 64K I$, 4 aliases possible, so we did
|
|
|
+ * flush start
|
|
|
+ * flush start | 0x01
|
|
|
+ * flush start | 0x2
|
|
|
+ * flush start | 0x3
|
|
|
+ *
|
|
|
+ * The penalty was invoking the operation itself, since tag match is anyways
|
|
|
+ * paddr based, a line which didn't represent an alias would not match the
|
|
|
+ * paddr, hence wont be killed
|
|
|
+ *
|
|
|
+ * Note that aliasing concerns are independent of line-sz for a given cache
|
|
|
+ * geometry (size + set_assoc) because the extra bits required by line-sz are
|
|
|
+ * reduced from the set calc.
|
|
|
+ * e.g. 2-way-set-assoc, 32K I$ with 8k MMU pg sz and using math above
|
|
|
+ * 32b line-sz: 9 bits set-index-calc, 5 bits offset-in-line => 1 extra bit
|
|
|
+ * 64b line-sz: 8 bits set-index-calc, 6 bits offset-in-line => 1 extra bit
|
|
|
+ *
|
|
|
+ * ------------------
|
|
|
+ * MMU v3
|
|
|
+ * ------------------
|
|
|
+ * This ver of MMU supports var page sizes (1k-16k) - Linux will support
|
|
|
+ * 8k (default), 16k and 4k.
|
|
|
+ * However from hardware perspective, smaller page sizes aggrevate aliasing
|
|
|
+ * meaning more vaddr bits needed to disambiguate the cache-line-op ;
|
|
|
+ * the existing scheme of piggybacking won't work for certain configurations.
|
|
|
+ * Two new registers IC_PTAG and DC_PTAG inttoduced.
|
|
|
+ * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
|
|
|
+ */
|
|
|
+
|
|
|
+/***********************************************************
|
|
|
+ * Machine specific helpers for per line I-Cache invalidate.
|
|
|
+ * 3 routines to accpunt for 1, 2, 4 aliases possible
|
|
|
+ */
|
|
|
+
|
|
|
+static void __ic_line_inv_no_alias(unsigned long start, int num_lines)
|
|
|
+{
|
|
|
+ while (num_lines-- > 0) {
|
|
|
+#if (CONFIG_ARC_MMU_VER > 2)
|
|
|
+ write_aux_reg(ARC_REG_IC_PTAG, start);
|
|
|
+#endif
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL, start);
|
|
|
+ start += ARC_ICACHE_LINE_LEN;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void __ic_line_inv_2_alias(unsigned long start, int num_lines)
|
|
|
+{
|
|
|
+ while (num_lines-- > 0) {
|
|
|
+
|
|
|
+#if (CONFIG_ARC_MMU_VER > 2)
|
|
|
+ /*
|
|
|
+ * MMU v3, CDU prog model (for line ops) now uses a new IC_PTAG
|
|
|
+ * reg to pass the "tag" bits and existing IVIL reg only looks
|
|
|
+ * at bits relevant for "index" (details above)
|
|
|
+ * Programming Notes:
|
|
|
+ * -when writing tag to PTAG reg, bit chopping can be avoided,
|
|
|
+ * CDU ignores non-tag bits.
|
|
|
+ * -Ideally "index" must be computed from vaddr, but it is not
|
|
|
+ * avail in these rtns. So to be safe, we kill the lines in all
|
|
|
+ * possible indexes corresp to num of aliases possible for
|
|
|
+ * given cache config.
|
|
|
+ */
|
|
|
+ write_aux_reg(ARC_REG_IC_PTAG, start);
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL,
|
|
|
+ start & ~(0x1 << PAGE_SHIFT));
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL, start | (0x1 << PAGE_SHIFT));
|
|
|
+#else
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL, start);
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL, start | 0x01);
|
|
|
+#endif
|
|
|
+ start += ARC_ICACHE_LINE_LEN;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void __ic_line_inv_4_alias(unsigned long start, int num_lines)
|
|
|
+{
|
|
|
+ while (num_lines-- > 0) {
|
|
|
+
|
|
|
+#if (CONFIG_ARC_MMU_VER > 2)
|
|
|
+ write_aux_reg(ARC_REG_IC_PTAG, start);
|
|
|
+
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL,
|
|
|
+ start & ~(0x3 << PAGE_SHIFT));
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL,
|
|
|
+ start & ~(0x2 << PAGE_SHIFT));
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL,
|
|
|
+ start & ~(0x1 << PAGE_SHIFT));
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL, start | (0x3 << PAGE_SHIFT));
|
|
|
+#else
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL, start);
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL, start | 0x01);
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL, start | 0x02);
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL, start | 0x03);
|
|
|
+#endif
|
|
|
+ start += ARC_ICACHE_LINE_LEN;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void __ic_line_inv(unsigned long start, unsigned long sz)
|
|
|
+{
|
|
|
+ unsigned long flags;
|
|
|
+ int num_lines, slack;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Ensure we properly floor/ceil the non-line aligned/sized requests
|
|
|
+ * and have @start - aligned to cache line, and integral @num_lines
|
|
|
+ * However page sized flushes can be compile time optimised.
|
|
|
+ * -@start will be cache-line aligned already (being page aligned)
|
|
|
+ * -@sz will be integral multiple of line size (being page sized).
|
|
|
+ */
|
|
|
+ if (!(__builtin_constant_p(sz) && sz == PAGE_SIZE)) {
|
|
|
+ slack = start & ~ICACHE_LINE_MASK;
|
|
|
+ sz += slack;
|
|
|
+ start -= slack;
|
|
|
+ }
|
|
|
+
|
|
|
+ num_lines = DIV_ROUND_UP(sz, ARC_ICACHE_LINE_LEN);
|
|
|
+
|
|
|
+ local_irq_save(flags);
|
|
|
+ (*___flush_icache_rtn) (start, num_lines);
|
|
|
+ local_irq_restore(flags);
|
|
|
+}
|
|
|
+
|
|
|
+/* Unlike routines above, having vaddr for flush op (along with paddr),
|
|
|
+ * prevents the need to speculatively kill the lines in multiple sets
|
|
|
+ * based on ratio of way_sz : pg_sz
|
|
|
+ */
|
|
|
+static void __ic_line_inv_vaddr(unsigned long phy_start,
|
|
|
+ unsigned long vaddr, unsigned long sz)
|
|
|
+{
|
|
|
+ unsigned long flags;
|
|
|
+ int num_lines, slack;
|
|
|
+ unsigned int addr;
|
|
|
+
|
|
|
+ slack = phy_start & ~ICACHE_LINE_MASK;
|
|
|
+ sz += slack;
|
|
|
+ phy_start -= slack;
|
|
|
+ num_lines = DIV_ROUND_UP(sz, ARC_ICACHE_LINE_LEN);
|
|
|
+
|
|
|
+#if (CONFIG_ARC_MMU_VER > 2)
|
|
|
+ vaddr &= ~ICACHE_LINE_MASK;
|
|
|
+ addr = phy_start;
|
|
|
+#else
|
|
|
+ /* bits 17:13 of vaddr go as bits 4:0 of paddr */
|
|
|
+ addr = phy_start | ((vaddr >> 13) & 0x1F);
|
|
|
+#endif
|
|
|
+
|
|
|
+ local_irq_save(flags);
|
|
|
+ while (num_lines-- > 0) {
|
|
|
+#if (CONFIG_ARC_MMU_VER > 2)
|
|
|
+ /* tag comes from phy addr */
|
|
|
+ write_aux_reg(ARC_REG_IC_PTAG, addr);
|
|
|
+
|
|
|
+ /* index bits come from vaddr */
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL, vaddr);
|
|
|
+ vaddr += ARC_ICACHE_LINE_LEN;
|
|
|
+#else
|
|
|
+ /* this paddr contains vaddrs bits as needed */
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIL, addr);
|
|
|
+#endif
|
|
|
+ addr += ARC_ICACHE_LINE_LEN;
|
|
|
+ }
|
|
|
+ local_irq_restore(flags);
|
|
|
+}
|
|
|
+
|
|
|
+#else
|
|
|
+
|
|
|
+#define __ic_line_inv(start, sz)
|
|
|
+#define __ic_line_inv_vaddr(pstart, vstart, sz)
|
|
|
+
|
|
|
+#endif /* CONFIG_ARC_HAS_ICACHE */
|
|
|
+
|
|
|
+
|
|
|
+/***********************************************************
|
|
|
+ * Exported APIs
|
|
|
+ */
|
|
|
+
|
|
|
+/* TBD: use pg_arch_1 to optimize this */
|
|
|
+void flush_dcache_page(struct page *page)
|
|
|
+{
|
|
|
+ __dc_line_op((unsigned long)page_address(page), PAGE_SIZE, OP_FLUSH);
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(flush_dcache_page);
|
|
|
+
|
|
|
+
|
|
|
+void dma_cache_wback_inv(unsigned long start, unsigned long sz)
|
|
|
+{
|
|
|
+ __dc_line_op(start, sz, OP_FLUSH_N_INV);
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(dma_cache_wback_inv);
|
|
|
+
|
|
|
+void dma_cache_inv(unsigned long start, unsigned long sz)
|
|
|
+{
|
|
|
+ __dc_line_op(start, sz, OP_INV);
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(dma_cache_inv);
|
|
|
+
|
|
|
+void dma_cache_wback(unsigned long start, unsigned long sz)
|
|
|
+{
|
|
|
+ __dc_line_op(start, sz, OP_FLUSH);
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(dma_cache_wback);
|
|
|
+
|
|
|
+/*
|
|
|
+ * This is API for making I/D Caches consistent when modifying code
|
|
|
+ * (loadable modules, kprobes, etc)
|
|
|
+ * This is called on insmod, with kernel virtual address for CODE of
|
|
|
+ * the module. ARC cache maintenance ops require PHY address thus we
|
|
|
+ * need to convert vmalloc addr to PHY addr
|
|
|
+ */
|
|
|
+void flush_icache_range(unsigned long kstart, unsigned long kend)
|
|
|
+{
|
|
|
+ unsigned int tot_sz, off, sz;
|
|
|
+ unsigned long phy, pfn;
|
|
|
+ unsigned long flags;
|
|
|
+
|
|
|
+ /* printk("Kernel Cache Cohenercy: %lx to %lx\n",kstart, kend); */
|
|
|
+
|
|
|
+ /* This is not the right API for user virtual address */
|
|
|
+ if (kstart < TASK_SIZE) {
|
|
|
+ BUG_ON("Flush icache range for user virtual addr space");
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Shortcut for bigger flush ranges.
|
|
|
+ * Here we don't care if this was kernel virtual or phy addr
|
|
|
+ */
|
|
|
+ tot_sz = kend - kstart;
|
|
|
+ if (tot_sz > PAGE_SIZE) {
|
|
|
+ flush_cache_all();
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Case: Kernel Phy addr (0x8000_0000 onwards) */
|
|
|
+ if (likely(kstart > PAGE_OFFSET)) {
|
|
|
+ __ic_line_inv(kstart, kend - kstart);
|
|
|
+ __dc_line_op(kstart, kend - kstart, OP_FLUSH);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff)
|
|
|
+ * (1) ARC Cache Maintenance ops only take Phy addr, hence special
|
|
|
+ * handling of kernel vaddr.
|
|
|
+ *
|
|
|
+ * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already),
|
|
|
+ * it still needs to handle a 2 page scenario, where the range
|
|
|
+ * straddles across 2 virtual pages and hence need for loop
|
|
|
+ */
|
|
|
+ while (tot_sz > 0) {
|
|
|
+ off = kstart % PAGE_SIZE;
|
|
|
+ pfn = vmalloc_to_pfn((void *)kstart);
|
|
|
+ phy = (pfn << PAGE_SHIFT) + off;
|
|
|
+ sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off);
|
|
|
+ local_irq_save(flags);
|
|
|
+ __dc_line_op(phy, sz, OP_FLUSH);
|
|
|
+ __ic_line_inv(phy, sz);
|
|
|
+ local_irq_restore(flags);
|
|
|
+ kstart += sz;
|
|
|
+ tot_sz -= sz;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * Optimised ver of flush_icache_range() with spec callers: ptrace/signals
|
|
|
+ * where vaddr is also available. This allows passing both vaddr and paddr
|
|
|
+ * bits to CDU for cache flush, short-circuting the current pessimistic algo
|
|
|
+ * which kills all possible aliases.
|
|
|
+ * An added adv of knowing that vaddr is user-vaddr avoids various checks
|
|
|
+ * and handling for k-vaddr, k-paddr as done in orig ver above
|
|
|
+ */
|
|
|
+void flush_icache_range_vaddr(unsigned long paddr, unsigned long u_vaddr,
|
|
|
+ int len)
|
|
|
+{
|
|
|
+ __ic_line_inv_vaddr(paddr, u_vaddr, len);
|
|
|
+ __dc_line_op(paddr, len, OP_FLUSH);
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * XXX: This also needs to be optim using pg_arch_1
|
|
|
+ * This is called when a page-cache page is about to be mapped into a
|
|
|
+ * user process' address space. It offers an opportunity for a
|
|
|
+ * port to ensure d-cache/i-cache coherency if necessary.
|
|
|
+ */
|
|
|
+void flush_icache_page(struct vm_area_struct *vma, struct page *page)
|
|
|
+{
|
|
|
+ if (!(vma->vm_flags & VM_EXEC))
|
|
|
+ return;
|
|
|
+
|
|
|
+ __ic_line_inv((unsigned long)page_address(page), PAGE_SIZE);
|
|
|
+}
|
|
|
+
|
|
|
+void flush_icache_all(void)
|
|
|
+{
|
|
|
+ unsigned long flags;
|
|
|
+
|
|
|
+ local_irq_save(flags);
|
|
|
+
|
|
|
+ write_aux_reg(ARC_REG_IC_IVIC, 1);
|
|
|
+
|
|
|
+ /* lr will not complete till the icache inv operation is not over */
|
|
|
+ read_aux_reg(ARC_REG_IC_CTRL);
|
|
|
+ local_irq_restore(flags);
|
|
|
+}
|
|
|
+
|
|
|
+noinline void flush_cache_all(void)
|
|
|
+{
|
|
|
+ unsigned long flags;
|
|
|
+
|
|
|
+ local_irq_save(flags);
|
|
|
+
|
|
|
+ flush_icache_all();
|
|
|
+ __dc_entire_op(OP_FLUSH_N_INV);
|
|
|
+
|
|
|
+ local_irq_restore(flags);
|
|
|
+
|
|
|
+}
|
|
|
+
|
|
|
+/**********************************************************************
|
|
|
+ * Explicit Cache flush request from user space via syscall
|
|
|
+ * Needed for JITs which generate code on the fly
|
|
|
+ */
|
|
|
+SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
|
|
|
+{
|
|
|
+ /* TBD: optimize this */
|
|
|
+ flush_cache_all();
|
|
|
+ return 0;
|
|
|
+}
|
Vineet Gupta