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@@ -271,8 +271,10 @@ enum {
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#define NVREG_LINKSPEED_MASK (0xFFF)
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NvRegUnknownSetupReg5 = 0x130,
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#define NVREG_UNKSETUP5_BIT31 (1<<31)
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- NvRegUnknownSetupReg3 = 0x13c,
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-#define NVREG_UNKSETUP3_VAL1 0x200010
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+ NvRegTxWatermark = 0x13c,
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+#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
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+#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
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+#define NVREG_TX_WM_DESC2_3_1000 0xfe08000
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NvRegTxRxControl = 0x144,
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#define NVREG_TXRXCTL_KICK 0x0001
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#define NVREG_TXRXCTL_BIT1 0x0002
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@@ -660,7 +662,7 @@ static const struct register_test nv_registers_test[] = {
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{ NvRegMisc1, 0x03c },
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{ NvRegOffloadConfig, 0x03ff },
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{ NvRegMulticastAddrA, 0xffffffff },
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- { NvRegUnknownSetupReg3, 0x0ff },
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+ { NvRegTxWatermark, 0x0ff },
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{ NvRegWakeUpFlags, 0x07777 },
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{ 0,0 }
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};
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@@ -2257,6 +2259,16 @@ set_speed:
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}
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writel(txreg, base + NvRegTxDeferral);
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+ if (np->desc_ver == DESC_VER_1) {
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+ txreg = NVREG_TX_WM_DESC1_DEFAULT;
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+ } else {
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+ if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
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+ txreg = NVREG_TX_WM_DESC2_3_1000;
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+ else
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+ txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
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+ }
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+ writel(txreg, base + NvRegTxWatermark);
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+
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writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
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base + NvRegMisc1);
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pci_push(base);
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@@ -3922,7 +3934,10 @@ static int nv_open(struct net_device *dev)
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/* 5) continue setup */
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writel(np->linkspeed, base + NvRegLinkSpeed);
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- writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
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+ if (np->desc_ver == DESC_VER_1)
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+ writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
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+ else
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+ writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
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writel(np->txrxctl_bits, base + NvRegTxRxControl);
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writel(np->vlanctl_bits, base + NvRegVlanControl);
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pci_push(base);
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