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@@ -525,16 +525,206 @@ static int mb86a20s_set_frontend(struct dvb_frontend *fe)
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return rc;
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}
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+static int mb86a20s_get_modulation(struct mb86a20s_state *state,
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+ unsigned layer)
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+{
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+ int rc;
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+ static unsigned char reg[] = {
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+ [0] = 0x86, /* Layer A */
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+ [1] = 0x8a, /* Layer B */
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+ [2] = 0x8e, /* Layer C */
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+ };
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+
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+ if (layer > ARRAY_SIZE(reg))
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+ return -EINVAL;
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+ rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
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+ if (rc < 0)
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+ return rc;
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+ rc = mb86a20s_readreg(state, 0x6e);
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+ if (rc < 0)
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+ return rc;
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+ switch ((rc & 0x70) >> 4) {
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+ case 0:
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+ return DQPSK;
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+ case 1:
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+ return QPSK;
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+ case 2:
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+ return QAM_16;
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+ case 3:
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+ return QAM_64;
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+ default:
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+ return QAM_AUTO;
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+ }
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+}
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+
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+static int mb86a20s_get_fec(struct mb86a20s_state *state,
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+ unsigned layer)
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+{
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+ int rc;
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+
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+ static unsigned char reg[] = {
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+ [0] = 0x87, /* Layer A */
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+ [1] = 0x8b, /* Layer B */
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+ [2] = 0x8f, /* Layer C */
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+ };
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+
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+ if (layer > ARRAY_SIZE(reg))
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+ return -EINVAL;
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+ rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
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+ if (rc < 0)
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+ return rc;
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+ rc = mb86a20s_readreg(state, 0x6e);
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+ if (rc < 0)
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+ return rc;
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+ switch (rc) {
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+ case 0:
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+ return FEC_1_2;
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+ case 1:
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+ return FEC_2_3;
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+ case 2:
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+ return FEC_3_4;
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+ case 3:
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+ return FEC_5_6;
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+ case 4:
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+ return FEC_7_8;
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+ default:
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+ return FEC_AUTO;
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+ }
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+}
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+
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+static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
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+ unsigned layer)
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+{
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+ int rc;
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+
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+ static unsigned char reg[] = {
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+ [0] = 0x88, /* Layer A */
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+ [1] = 0x8c, /* Layer B */
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+ [2] = 0x90, /* Layer C */
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+ };
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+
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+ if (layer > ARRAY_SIZE(reg))
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+ return -EINVAL;
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+ rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
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+ if (rc < 0)
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+ return rc;
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+ rc = mb86a20s_readreg(state, 0x6e);
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+ if (rc < 0)
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+ return rc;
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+ if (rc > 3)
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+ return -EINVAL; /* Not used */
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+ return rc;
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+}
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+
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+static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
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+ unsigned layer)
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+{
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+ int rc, count;
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+
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+ static unsigned char reg[] = {
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+ [0] = 0x89, /* Layer A */
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+ [1] = 0x8d, /* Layer B */
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+ [2] = 0x91, /* Layer C */
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+ };
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+
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+ if (layer > ARRAY_SIZE(reg))
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+ return -EINVAL;
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+ rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
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+ if (rc < 0)
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+ return rc;
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+ rc = mb86a20s_readreg(state, 0x6e);
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+ if (rc < 0)
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+ return rc;
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+ count = (rc >> 4) & 0x0f;
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+
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+ return count;
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+}
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+
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static int mb86a20s_get_frontend(struct dvb_frontend *fe)
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{
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+ struct mb86a20s_state *state = fe->demodulator_priv;
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struct dtv_frontend_properties *p = &fe->dtv_property_cache;
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+ int i, rc;
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- /* FIXME: For now, it does nothing */
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-
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+ /* Fixed parameters */
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+ p->delivery_system = SYS_ISDBT;
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p->bandwidth_hz = 6000000;
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+
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+ if (fe->ops.i2c_gate_ctrl)
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+ fe->ops.i2c_gate_ctrl(fe, 0);
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+
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+ /* Check for partial reception */
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+ rc = mb86a20s_writereg(state, 0x6d, 0x85);
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+ if (rc >= 0)
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+ rc = mb86a20s_readreg(state, 0x6e);
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+ if (rc >= 0)
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+ p->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
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+
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+ /* Get per-layer data */
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+ p->isdbt_layer_enabled = 0;
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+ for (i = 0; i < 3; i++) {
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+ rc = mb86a20s_get_segment_count(state, i);
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+ if (rc >= 0 && rc < 14)
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+ p->layer[i].segment_count = rc;
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+ if (rc == 0x0f)
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+ continue;
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+ p->isdbt_layer_enabled |= 1 << i;
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+ rc = mb86a20s_get_modulation(state, i);
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+ if (rc >= 0)
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+ p->layer[i].modulation = rc;
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+ rc = mb86a20s_get_fec(state, i);
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+ if (rc >= 0)
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+ p->layer[i].fec = rc;
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+ rc = mb86a20s_get_interleaving(state, i);
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+ if (rc >= 0)
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+ p->layer[i].interleaving = rc;
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+ }
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+
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+ p->isdbt_sb_mode = 0;
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+ rc = mb86a20s_writereg(state, 0x6d, 0x84);
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+ if ((rc >= 0) && ((rc & 0x60) == 0x20)) {
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+ p->isdbt_sb_mode = 1;
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+ /* At least, one segment should exist */
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+ if (!p->isdbt_sb_segment_count)
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+ p->isdbt_sb_segment_count = 1;
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+ } else
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+ p->isdbt_sb_segment_count = 0;
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+
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+ /* Get transmission mode and guard interval */
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p->transmission_mode = TRANSMISSION_MODE_AUTO;
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p->guard_interval = GUARD_INTERVAL_AUTO;
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- p->isdbt_partial_reception = 0;
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+ rc = mb86a20s_readreg(state, 0x07);
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+ if (rc >= 0) {
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+ if ((rc & 0x60) == 0x20) {
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+ switch (rc & 0x0c >> 2) {
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+ case 0:
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+ p->transmission_mode = TRANSMISSION_MODE_2K;
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+ break;
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+ case 1:
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+ p->transmission_mode = TRANSMISSION_MODE_4K;
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+ break;
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+ case 2:
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+ p->transmission_mode = TRANSMISSION_MODE_8K;
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+ break;
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+ }
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+ }
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+ if (!(rc & 0x10)) {
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+ switch (rc & 0x3) {
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+ case 0:
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+ p->guard_interval = GUARD_INTERVAL_1_4;
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+ break;
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+ case 1:
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+ p->guard_interval = GUARD_INTERVAL_1_8;
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+ break;
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+ case 2:
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+ p->guard_interval = GUARD_INTERVAL_1_16;
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+ break;
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+ }
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+ }
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+ }
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+
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+ if (fe->ops.i2c_gate_ctrl)
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+ fe->ops.i2c_gate_ctrl(fe, 1);
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return 0;
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}
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