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@@ -223,12 +223,6 @@ ia64_phys_addr_valid (unsigned long addr)
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* page table.
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*/
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-/*
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- * On some architectures, special things need to be done when setting
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- * the PTE in a page table. Nothing special needs to be on IA-64.
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- */
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-#define set_pte(ptep, pteval) (*(ptep) = (pteval))
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-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
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#define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL)
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#ifdef CONFIG_VIRTUAL_MEM_MAP
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@@ -320,6 +314,36 @@ ia64_phys_addr_valid (unsigned long addr)
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#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
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#define pte_mkhuge(pte) (__pte(pte_val(pte)))
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+/*
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+ * Because ia64's Icache and Dcache is not coherent (on a cpu), we need to
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+ * sync icache and dcache when we insert *new* executable page.
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+ * __ia64_sync_icache_dcache() check Pg_arch_1 bit and flush icache
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+ * if necessary.
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+ *
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+ * set_pte() is also called by the kernel, but we can expect that the kernel
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+ * flushes icache explicitly if necessary.
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+ */
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+#define pte_present_exec_user(pte)\
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+ ((pte_val(pte) & (_PAGE_P | _PAGE_PL_MASK | _PAGE_AR_RX)) == \
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+ (_PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX))
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+
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+extern void __ia64_sync_icache_dcache(pte_t pteval);
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+static inline void set_pte(pte_t *ptep, pte_t pteval)
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+{
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+ /* page is present && page is user && page is executable
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+ * && (page swapin or new page or page migraton
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+ * || copy_on_write with page copying.)
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+ */
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+ if (pte_present_exec_user(pteval) &&
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+ (!pte_present(*ptep) ||
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+ pte_pfn(*ptep) != pte_pfn(pteval)))
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+ /* load_module() calles flush_icache_range() explicitly*/
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+ __ia64_sync_icache_dcache(pteval);
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+ *ptep = pteval;
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+}
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+
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+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
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+
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/*
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* Make page protection values cacheable, uncacheable, or write-
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* combining. Note that "protection" is really a misnomer here as the
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@@ -489,12 +513,6 @@ extern struct page *zero_page_memmap_ptr;
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#define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1))
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#endif
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-/*
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- * IA-64 doesn't have any external MMU info: the page tables contain all the necessary
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- * information. However, we use this routine to take care of any (delayed) i-cache
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- * flushing that may be necessary.
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- */
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-extern void lazy_mmu_prot_update (pte_t pte);
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#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
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/*
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@@ -584,7 +602,7 @@ extern void lazy_mmu_prot_update (pte_t pte);
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#define __HAVE_ARCH_PTEP_SET_WRPROTECT
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#define __HAVE_ARCH_PTE_SAME
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#define __HAVE_ARCH_PGD_OFFSET_GATE
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-#define __HAVE_ARCH_LAZY_MMU_PROT_UPDATE
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+
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#ifndef CONFIG_PGTABLE_4
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#include <asm-generic/pgtable-nopud.h>
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