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@@ -98,17 +98,48 @@ struct context;
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typedef int (*descriptor_callback_t)(struct context *ctx,
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struct descriptor *d,
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struct descriptor *last);
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+
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+/*
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+ * A buffer that contains a block of DMA-able coherent memory used for
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+ * storing a portion of a DMA descriptor program.
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+ */
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+struct descriptor_buffer {
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+ struct list_head list;
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+ dma_addr_t buffer_bus;
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+ size_t buffer_size;
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+ size_t used;
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+ struct descriptor buffer[0];
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+};
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+
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struct context {
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struct fw_ohci *ohci;
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u32 regs;
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+ int total_allocation;
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- struct descriptor *buffer;
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- dma_addr_t buffer_bus;
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- size_t buffer_size;
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- struct descriptor *head_descriptor;
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- struct descriptor *tail_descriptor;
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- struct descriptor *tail_descriptor_last;
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- struct descriptor *prev_descriptor;
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+ /*
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+ * List of page-sized buffers for storing DMA descriptors.
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+ * Head of list contains buffers in use and tail of list contains
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+ * free buffers.
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+ */
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+ struct list_head buffer_list;
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+
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+ /*
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+ * Pointer to a buffer inside buffer_list that contains the tail
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+ * end of the current DMA program.
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+ */
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+ struct descriptor_buffer *buffer_tail;
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+
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+ /*
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+ * The descriptor containing the branch address of the first
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+ * descriptor that has not yet been filled by the device.
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+ */
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+ struct descriptor *last;
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+
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+ /*
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+ * The last descriptor in the DMA program. It contains the branch
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+ * address that must be updated upon appending a new descriptor.
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+ */
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+ struct descriptor *prev;
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descriptor_callback_t callback;
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@@ -125,6 +156,7 @@ struct context {
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struct iso_context {
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struct fw_iso_context base;
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struct context context;
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+ int excess_bytes;
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void *header;
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size_t header_length;
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};
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@@ -197,8 +229,6 @@ static inline struct fw_ohci *fw_ohci(struct fw_card *card)
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#define SELF_ID_BUF_SIZE 0x800
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#define OHCI_TCODE_PHY_PACKET 0x0e
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#define OHCI_VERSION_1_1 0x010010
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-#define ISO_BUFFER_SIZE (64 * 1024)
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-#define AT_BUFFER_SIZE 4096
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static char ohci_driver_name[] = KBUILD_MODNAME;
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@@ -455,71 +485,108 @@ find_branch_descriptor(struct descriptor *d, int z)
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static void context_tasklet(unsigned long data)
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{
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struct context *ctx = (struct context *) data;
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- struct fw_ohci *ohci = ctx->ohci;
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struct descriptor *d, *last;
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u32 address;
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int z;
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+ struct descriptor_buffer *desc;
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- dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
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- ctx->buffer_size, DMA_TO_DEVICE);
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-
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- d = ctx->tail_descriptor;
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- last = ctx->tail_descriptor_last;
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-
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+ desc = list_entry(ctx->buffer_list.next,
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+ struct descriptor_buffer, list);
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+ last = ctx->last;
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while (last->branch_address != 0) {
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+ struct descriptor_buffer *old_desc = desc;
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address = le32_to_cpu(last->branch_address);
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z = address & 0xf;
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- d = ctx->buffer + (address - ctx->buffer_bus) / sizeof(*d);
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+ address &= ~0xf;
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+
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+ /* If the branch address points to a buffer outside of the
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+ * current buffer, advance to the next buffer. */
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+ if (address < desc->buffer_bus ||
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+ address >= desc->buffer_bus + desc->used)
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+ desc = list_entry(desc->list.next,
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+ struct descriptor_buffer, list);
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+ d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
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last = find_branch_descriptor(d, z);
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if (!ctx->callback(ctx, d, last))
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break;
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- ctx->tail_descriptor = d;
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- ctx->tail_descriptor_last = last;
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+ if (old_desc != desc) {
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+ /* If we've advanced to the next buffer, move the
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+ * previous buffer to the free list. */
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+ unsigned long flags;
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+ old_desc->used = 0;
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+ spin_lock_irqsave(&ctx->ohci->lock, flags);
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+ list_move_tail(&old_desc->list, &ctx->buffer_list);
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+ spin_unlock_irqrestore(&ctx->ohci->lock, flags);
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+ }
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+ ctx->last = last;
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}
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}
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+/*
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+ * Allocate a new buffer and add it to the list of free buffers for this
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+ * context. Must be called with ohci->lock held.
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+ */
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+static int
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+context_add_buffer(struct context *ctx)
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+{
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+ struct descriptor_buffer *desc;
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+ dma_addr_t bus_addr;
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+ int offset;
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+
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+ /*
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+ * 16MB of descriptors should be far more than enough for any DMA
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+ * program. This will catch run-away userspace or DoS attacks.
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+ */
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+ if (ctx->total_allocation >= 16*1024*1024)
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+ return -ENOMEM;
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+
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+ desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
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+ &bus_addr, GFP_ATOMIC);
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+ if (!desc)
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+ return -ENOMEM;
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+
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+ offset = (void *)&desc->buffer - (void *)desc;
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+ desc->buffer_size = PAGE_SIZE - offset;
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+ desc->buffer_bus = bus_addr + offset;
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+ desc->used = 0;
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+
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+ list_add_tail(&desc->list, &ctx->buffer_list);
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+ ctx->total_allocation += PAGE_SIZE;
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+
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+ return 0;
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+}
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+
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static int
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context_init(struct context *ctx, struct fw_ohci *ohci,
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- size_t buffer_size, u32 regs,
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- descriptor_callback_t callback)
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+ u32 regs, descriptor_callback_t callback)
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{
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ctx->ohci = ohci;
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ctx->regs = regs;
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- ctx->buffer_size = buffer_size;
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- ctx->buffer = kmalloc(buffer_size, GFP_KERNEL);
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- if (ctx->buffer == NULL)
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+ ctx->total_allocation = 0;
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+
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+ INIT_LIST_HEAD(&ctx->buffer_list);
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+ if (context_add_buffer(ctx) < 0)
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return -ENOMEM;
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+ ctx->buffer_tail = list_entry(ctx->buffer_list.next,
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+ struct descriptor_buffer, list);
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+
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tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
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ctx->callback = callback;
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- ctx->buffer_bus =
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- dma_map_single(ohci->card.device, ctx->buffer,
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- buffer_size, DMA_TO_DEVICE);
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- if (dma_mapping_error(ctx->buffer_bus)) {
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- kfree(ctx->buffer);
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- return -ENOMEM;
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- }
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-
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- ctx->head_descriptor = ctx->buffer;
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- ctx->prev_descriptor = ctx->buffer;
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- ctx->tail_descriptor = ctx->buffer;
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- ctx->tail_descriptor_last = ctx->buffer;
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-
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/*
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* We put a dummy descriptor in the buffer that has a NULL
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* branch address and looks like it's been sent. That way we
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- * have a descriptor to append DMA programs to. Also, the
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- * ring buffer invariant is that it always has at least one
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- * element so that head == tail means buffer full.
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+ * have a descriptor to append DMA programs to.
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*/
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-
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- memset(ctx->head_descriptor, 0, sizeof(*ctx->head_descriptor));
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- ctx->head_descriptor->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
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- ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
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- ctx->head_descriptor++;
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+ memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
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+ ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
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+ ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
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+ ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
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+ ctx->last = ctx->buffer_tail->buffer;
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+ ctx->prev = ctx->buffer_tail->buffer;
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return 0;
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}
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@@ -528,35 +595,42 @@ static void
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context_release(struct context *ctx)
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{
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struct fw_card *card = &ctx->ohci->card;
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+ struct descriptor_buffer *desc, *tmp;
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- dma_unmap_single(card->device, ctx->buffer_bus,
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- ctx->buffer_size, DMA_TO_DEVICE);
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- kfree(ctx->buffer);
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+ list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
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+ dma_free_coherent(card->device, PAGE_SIZE, desc,
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+ desc->buffer_bus -
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+ ((void *)&desc->buffer - (void *)desc));
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}
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+/* Must be called with ohci->lock held */
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static struct descriptor *
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context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
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{
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- struct descriptor *d, *tail, *end;
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-
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- d = ctx->head_descriptor;
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- tail = ctx->tail_descriptor;
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- end = ctx->buffer + ctx->buffer_size / sizeof(*d);
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-
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- if (d + z <= tail) {
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- goto has_space;
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- } else if (d > tail && d + z <= end) {
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- goto has_space;
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- } else if (d > tail && ctx->buffer + z <= tail) {
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- d = ctx->buffer;
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- goto has_space;
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- }
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+ struct descriptor *d = NULL;
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+ struct descriptor_buffer *desc = ctx->buffer_tail;
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+
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+ if (z * sizeof(*d) > desc->buffer_size)
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+ return NULL;
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- return NULL;
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+ if (z * sizeof(*d) > desc->buffer_size - desc->used) {
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+ /* No room for the descriptor in this buffer, so advance to the
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+ * next one. */
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+
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+ if (desc->list.next == &ctx->buffer_list) {
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+ /* If there is no free buffer next in the list,
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+ * allocate one. */
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+ if (context_add_buffer(ctx) < 0)
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+ return NULL;
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+ }
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+ desc = list_entry(desc->list.next,
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+ struct descriptor_buffer, list);
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+ ctx->buffer_tail = desc;
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+ }
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- has_space:
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+ d = desc->buffer + desc->used / sizeof(*d);
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memset(d, 0, z * sizeof(*d));
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- *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
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+ *d_bus = desc->buffer_bus + desc->used;
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return d;
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}
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@@ -566,7 +640,7 @@ static void context_run(struct context *ctx, u32 extra)
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struct fw_ohci *ohci = ctx->ohci;
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reg_write(ohci, COMMAND_PTR(ctx->regs),
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- le32_to_cpu(ctx->tail_descriptor_last->branch_address));
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+ le32_to_cpu(ctx->last->branch_address));
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reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
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reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
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flush_writes(ohci);
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@@ -576,15 +650,13 @@ static void context_append(struct context *ctx,
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struct descriptor *d, int z, int extra)
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{
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dma_addr_t d_bus;
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+ struct descriptor_buffer *desc = ctx->buffer_tail;
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- d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
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+ d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
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- ctx->head_descriptor = d + z + extra;
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- ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
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- ctx->prev_descriptor = find_branch_descriptor(d, z);
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-
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- dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus,
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- ctx->buffer_size, DMA_TO_DEVICE);
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+ desc->used += (z + extra) * sizeof(*d);
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+ ctx->prev->branch_address = cpu_to_le32(d_bus | z);
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+ ctx->prev = find_branch_descriptor(d, z);
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reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
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flush_writes(ctx->ohci);
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@@ -1078,6 +1150,13 @@ static irqreturn_t irq_handler(int irq, void *data)
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if (unlikely(event & OHCI1394_postedWriteErr))
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fw_error("PCI posted write error\n");
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+ if (unlikely(event & OHCI1394_cycleTooLong)) {
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+ if (printk_ratelimit())
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+ fw_notify("isochronous cycle too long\n");
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+ reg_write(ohci, OHCI1394_LinkControlSet,
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+ OHCI1394_LinkControl_cycleMaster);
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+ }
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+
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if (event & OHCI1394_cycle64Seconds) {
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cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
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if ((cycle_time & 0x80000000) == 0)
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@@ -1151,8 +1230,8 @@ static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
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OHCI1394_RQPkt | OHCI1394_RSPkt |
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OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
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OHCI1394_isochRx | OHCI1394_isochTx |
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- OHCI1394_postedWriteErr | OHCI1394_cycle64Seconds |
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- OHCI1394_masterIntEnable);
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+ OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
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+ OHCI1394_cycle64Seconds | OHCI1394_masterIntEnable);
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/* Activate link_on bit and contender bit in our self ID packets.*/
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if (ohci_update_phy_reg(card, 4, 0,
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@@ -1408,9 +1487,13 @@ static int handle_ir_dualbuffer_packet(struct context *context,
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void *p, *end;
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int i;
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- if (db->first_res_count > 0 && db->second_res_count > 0)
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- /* This descriptor isn't done yet, stop iteration. */
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- return 0;
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+ if (db->first_res_count > 0 && db->second_res_count > 0) {
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+ if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
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+ /* This descriptor isn't done yet, stop iteration. */
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+ return 0;
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+ }
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+ ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
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+ }
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header_length = le16_to_cpu(db->first_req_count) -
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le16_to_cpu(db->first_res_count);
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@@ -1429,11 +1512,15 @@ static int handle_ir_dualbuffer_packet(struct context *context,
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*(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
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memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
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i += ctx->base.header_size;
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+ ctx->excess_bytes +=
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+ (le32_to_cpu(*(u32 *)(p + 4)) >> 16) & 0xffff;
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p += ctx->base.header_size + 4;
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}
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-
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ctx->header_length = i;
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+ ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
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+ le16_to_cpu(db->second_res_count);
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+
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if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
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ir_header = (__le32 *) (db + 1);
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ctx->base.callback(&ctx->base,
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@@ -1452,24 +1539,24 @@ static int handle_ir_packet_per_buffer(struct context *context,
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{
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struct iso_context *ctx =
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container_of(context, struct iso_context, context);
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- struct descriptor *pd = d + 1;
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+ struct descriptor *pd;
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__le32 *ir_header;
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- size_t header_length;
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- void *p, *end;
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- int i, z;
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+ void *p;
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+ int i;
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- if (pd->res_count == pd->req_count)
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+ for (pd = d; pd <= last; pd++) {
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+ if (pd->transfer_status)
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+ break;
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+ }
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+ if (pd > last)
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/* Descriptor(s) not done yet, stop iteration */
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return 0;
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- header_length = le16_to_cpu(d->req_count);
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-
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|
|
i = ctx->header_length;
|
|
|
- z = le32_to_cpu(pd->branch_address) & 0xf;
|
|
|
- p = d + z;
|
|
|
- end = p + header_length;
|
|
|
+ p = last + 1;
|
|
|
|
|
|
- while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
|
|
|
+ if (ctx->base.header_size > 0 &&
|
|
|
+ i + ctx->base.header_size <= PAGE_SIZE) {
|
|
|
/*
|
|
|
* The iso header is byteswapped to little endian by
|
|
|
* the controller, but the remaining header quadlets
|
|
|
@@ -1478,14 +1565,11 @@ static int handle_ir_packet_per_buffer(struct context *context,
|
|
|
*/
|
|
|
*(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
|
|
|
memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
|
|
|
- i += ctx->base.header_size;
|
|
|
- p += ctx->base.header_size + 4;
|
|
|
+ ctx->header_length += ctx->base.header_size;
|
|
|
}
|
|
|
|
|
|
- ctx->header_length = i;
|
|
|
-
|
|
|
- if (le16_to_cpu(pd->control) & DESCRIPTOR_IRQ_ALWAYS) {
|
|
|
- ir_header = (__le32 *) (d + z);
|
|
|
+ if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
|
|
|
+ ir_header = (__le32 *) p;
|
|
|
ctx->base.callback(&ctx->base,
|
|
|
le32_to_cpu(ir_header[0]) & 0xffff,
|
|
|
ctx->header_length, ctx->header,
|
|
|
@@ -1493,7 +1577,6 @@ static int handle_ir_packet_per_buffer(struct context *context,
|
|
|
ctx->header_length = 0;
|
|
|
}
|
|
|
|
|
|
-
|
|
|
return 1;
|
|
|
}
|
|
|
|
|
|
@@ -1559,8 +1642,7 @@ ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
|
|
|
if (ctx->header == NULL)
|
|
|
goto out;
|
|
|
|
|
|
- retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE,
|
|
|
- regs, callback);
|
|
|
+ retval = context_init(&ctx->context, ohci, regs, callback);
|
|
|
if (retval < 0)
|
|
|
goto out_with_header;
|
|
|
|
|
|
@@ -1775,19 +1857,6 @@ ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
|
|
|
* packet, retransmit or terminate..
|
|
|
*/
|
|
|
|
|
|
- if (packet->skip) {
|
|
|
- d = context_get_descriptors(&ctx->context, 2, &d_bus);
|
|
|
- if (d == NULL)
|
|
|
- return -ENOMEM;
|
|
|
-
|
|
|
- db = (struct db_descriptor *) d;
|
|
|
- db->control = cpu_to_le16(DESCRIPTOR_STATUS |
|
|
|
- DESCRIPTOR_BRANCH_ALWAYS |
|
|
|
- DESCRIPTOR_WAIT);
|
|
|
- db->first_size = cpu_to_le16(ctx->base.header_size + 4);
|
|
|
- context_append(&ctx->context, d, 2, 0);
|
|
|
- }
|
|
|
-
|
|
|
p = packet;
|
|
|
z = 2;
|
|
|
|
|
|
@@ -1815,11 +1884,18 @@ ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
|
|
|
db->control = cpu_to_le16(DESCRIPTOR_STATUS |
|
|
|
DESCRIPTOR_BRANCH_ALWAYS);
|
|
|
db->first_size = cpu_to_le16(ctx->base.header_size + 4);
|
|
|
- db->first_req_count = cpu_to_le16(header_size);
|
|
|
+ if (p->skip && rest == p->payload_length) {
|
|
|
+ db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
|
|
|
+ db->first_req_count = db->first_size;
|
|
|
+ } else {
|
|
|
+ db->first_req_count = cpu_to_le16(header_size);
|
|
|
+ }
|
|
|
db->first_res_count = db->first_req_count;
|
|
|
db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
|
|
|
|
|
|
- if (offset + rest < PAGE_SIZE)
|
|
|
+ if (p->skip && rest == p->payload_length)
|
|
|
+ length = 4;
|
|
|
+ else if (offset + rest < PAGE_SIZE)
|
|
|
length = rest;
|
|
|
else
|
|
|
length = PAGE_SIZE - offset;
|
|
|
@@ -1835,7 +1911,8 @@ ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
|
|
|
context_append(&ctx->context, d, z, header_z);
|
|
|
offset = (offset + length) & ~PAGE_MASK;
|
|
|
rest -= length;
|
|
|
- page++;
|
|
|
+ if (offset == 0)
|
|
|
+ page++;
|
|
|
}
|
|
|
|
|
|
return 0;
|
|
|
@@ -1849,67 +1926,70 @@ ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
|
|
|
{
|
|
|
struct iso_context *ctx = container_of(base, struct iso_context, base);
|
|
|
struct descriptor *d = NULL, *pd = NULL;
|
|
|
- struct fw_iso_packet *p;
|
|
|
+ struct fw_iso_packet *p = packet;
|
|
|
dma_addr_t d_bus, page_bus;
|
|
|
u32 z, header_z, rest;
|
|
|
- int i, page, offset, packet_count, header_size;
|
|
|
-
|
|
|
- if (packet->skip) {
|
|
|
- d = context_get_descriptors(&ctx->context, 1, &d_bus);
|
|
|
- if (d == NULL)
|
|
|
- return -ENOMEM;
|
|
|
-
|
|
|
- d->control = cpu_to_le16(DESCRIPTOR_STATUS |
|
|
|
- DESCRIPTOR_INPUT_LAST |
|
|
|
- DESCRIPTOR_BRANCH_ALWAYS |
|
|
|
- DESCRIPTOR_WAIT);
|
|
|
- context_append(&ctx->context, d, 1, 0);
|
|
|
- }
|
|
|
-
|
|
|
- /* one descriptor for header, one for payload */
|
|
|
- /* FIXME: handle cases where we need multiple desc. for payload */
|
|
|
- z = 2;
|
|
|
- p = packet;
|
|
|
+ int i, j, length;
|
|
|
+ int page, offset, packet_count, header_size, payload_per_buffer;
|
|
|
|
|
|
/*
|
|
|
* The OHCI controller puts the status word in the
|
|
|
* buffer too, so we need 4 extra bytes per packet.
|
|
|
*/
|
|
|
packet_count = p->header_length / ctx->base.header_size;
|
|
|
- header_size = packet_count * (ctx->base.header_size + 4);
|
|
|
+ header_size = ctx->base.header_size + 4;
|
|
|
|
|
|
/* Get header size in number of descriptors. */
|
|
|
header_z = DIV_ROUND_UP(header_size, sizeof(*d));
|
|
|
page = payload >> PAGE_SHIFT;
|
|
|
offset = payload & ~PAGE_MASK;
|
|
|
- rest = p->payload_length;
|
|
|
+ payload_per_buffer = p->payload_length / packet_count;
|
|
|
|
|
|
for (i = 0; i < packet_count; i++) {
|
|
|
/* d points to the header descriptor */
|
|
|
+ z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
|
|
|
d = context_get_descriptors(&ctx->context,
|
|
|
- z + header_z, &d_bus);
|
|
|
+ z + header_z, &d_bus);
|
|
|
if (d == NULL)
|
|
|
return -ENOMEM;
|
|
|
|
|
|
- d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE);
|
|
|
+ d->control = cpu_to_le16(DESCRIPTOR_STATUS |
|
|
|
+ DESCRIPTOR_INPUT_MORE);
|
|
|
+ if (p->skip && i == 0)
|
|
|
+ d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
|
|
|
d->req_count = cpu_to_le16(header_size);
|
|
|
d->res_count = d->req_count;
|
|
|
+ d->transfer_status = 0;
|
|
|
d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
|
|
|
|
|
|
- /* pd points to the payload descriptor */
|
|
|
- pd = d + 1;
|
|
|
+ rest = payload_per_buffer;
|
|
|
+ for (j = 1; j < z; j++) {
|
|
|
+ pd = d + j;
|
|
|
+ pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
|
|
|
+ DESCRIPTOR_INPUT_MORE);
|
|
|
+
|
|
|
+ if (offset + rest < PAGE_SIZE)
|
|
|
+ length = rest;
|
|
|
+ else
|
|
|
+ length = PAGE_SIZE - offset;
|
|
|
+ pd->req_count = cpu_to_le16(length);
|
|
|
+ pd->res_count = pd->req_count;
|
|
|
+ pd->transfer_status = 0;
|
|
|
+
|
|
|
+ page_bus = page_private(buffer->pages[page]);
|
|
|
+ pd->data_address = cpu_to_le32(page_bus + offset);
|
|
|
+
|
|
|
+ offset = (offset + length) & ~PAGE_MASK;
|
|
|
+ rest -= length;
|
|
|
+ if (offset == 0)
|
|
|
+ page++;
|
|
|
+ }
|
|
|
pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
|
|
|
DESCRIPTOR_INPUT_LAST |
|
|
|
DESCRIPTOR_BRANCH_ALWAYS);
|
|
|
- if (p->interrupt)
|
|
|
+ if (p->interrupt && i == packet_count - 1)
|
|
|
pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
|
|
|
|
|
|
- pd->req_count = cpu_to_le16(rest);
|
|
|
- pd->res_count = pd->req_count;
|
|
|
-
|
|
|
- page_bus = page_private(buffer->pages[page]);
|
|
|
- pd->data_address = cpu_to_le32(page_bus + offset);
|
|
|
-
|
|
|
context_append(&ctx->context, d, z, header_z);
|
|
|
}
|
|
|
|
|
|
@@ -1923,16 +2003,22 @@ ohci_queue_iso(struct fw_iso_context *base,
|
|
|
unsigned long payload)
|
|
|
{
|
|
|
struct iso_context *ctx = container_of(base, struct iso_context, base);
|
|
|
+ unsigned long flags;
|
|
|
+ int retval;
|
|
|
|
|
|
+ spin_lock_irqsave(&ctx->context.ohci->lock, flags);
|
|
|
if (base->type == FW_ISO_CONTEXT_TRANSMIT)
|
|
|
- return ohci_queue_iso_transmit(base, packet, buffer, payload);
|
|
|
+ retval = ohci_queue_iso_transmit(base, packet, buffer, payload);
|
|
|
else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
|
|
|
- return ohci_queue_iso_receive_dualbuffer(base, packet,
|
|
|
+ retval = ohci_queue_iso_receive_dualbuffer(base, packet,
|
|
|
buffer, payload);
|
|
|
else
|
|
|
- return ohci_queue_iso_receive_packet_per_buffer(base, packet,
|
|
|
+ retval = ohci_queue_iso_receive_packet_per_buffer(base, packet,
|
|
|
buffer,
|
|
|
payload);
|
|
|
+ spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
|
|
|
+
|
|
|
+ return retval;
|
|
|
}
|
|
|
|
|
|
static const struct fw_card_driver ohci_driver = {
|
|
|
@@ -2004,10 +2090,10 @@ pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
|
|
|
ar_context_init(&ohci->ar_response_ctx, ohci,
|
|
|
OHCI1394_AsRspRcvContextControlSet);
|
|
|
|
|
|
- context_init(&ohci->at_request_ctx, ohci, AT_BUFFER_SIZE,
|
|
|
+ context_init(&ohci->at_request_ctx, ohci,
|
|
|
OHCI1394_AsReqTrContextControlSet, handle_at_packet);
|
|
|
|
|
|
- context_init(&ohci->at_response_ctx, ohci, AT_BUFFER_SIZE,
|
|
|
+ context_init(&ohci->at_response_ctx, ohci,
|
|
|
OHCI1394_AsRspTrContextControlSet, handle_at_packet);
|
|
|
|
|
|
reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
|
Linus Torvalds