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@@ -260,12 +260,12 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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phy->reset_delay_us = 100;
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phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
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- phy->ops.read_phy_reg = e1000_read_phy_reg_hv;
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- phy->ops.read_phy_reg_locked = e1000_read_phy_reg_hv_locked;
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+ phy->ops.read_reg = e1000_read_phy_reg_hv;
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+ phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
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phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
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phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
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- phy->ops.write_phy_reg = e1000_write_phy_reg_hv;
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- phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked;
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+ phy->ops.write_reg = e1000_write_phy_reg_hv;
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+ phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
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phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
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phy->id = e1000_phy_unknown;
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@@ -277,8 +277,8 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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phy->ops.force_speed_duplex =
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e1000_phy_force_speed_duplex_82577;
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phy->ops.get_cable_length = e1000_get_cable_length_82577;
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- phy->ops.get_phy_info = e1000_get_phy_info_82577;
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- phy->ops.commit_phy = e1000e_phy_sw_reset;
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+ phy->ops.get_info = e1000_get_phy_info_82577;
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+ phy->ops.commit = e1000e_phy_sw_reset;
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}
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return ret_val;
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@@ -305,8 +305,8 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
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*/
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ret_val = e1000e_determine_phy_address(hw);
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if (ret_val) {
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- hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
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- hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
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+ phy->ops.write_reg = e1000e_write_phy_reg_bm;
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+ phy->ops.read_reg = e1000e_read_phy_reg_bm;
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ret_val = e1000e_determine_phy_address(hw);
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if (ret_val)
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return ret_val;
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@@ -326,8 +326,8 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
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case IGP03E1000_E_PHY_ID:
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phy->type = e1000_phy_igp_3;
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phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
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- phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked;
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- phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked;
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+ phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
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+ phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
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break;
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case IFE_E_PHY_ID:
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case IFE_PLUS_E_PHY_ID:
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@@ -338,9 +338,9 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
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case BME1000_E_PHY_ID:
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phy->type = e1000_phy_bm;
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phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
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- hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
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- hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
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- hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
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+ phy->ops.read_reg = e1000e_read_phy_reg_bm;
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+ phy->ops.write_reg = e1000e_write_phy_reg_bm;
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+ phy->ops.commit = e1000e_phy_sw_reset;
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break;
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default:
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return -E1000_ERR_PHY;
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@@ -816,7 +816,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
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s32 ret_val;
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u16 word_addr, reg_data, reg_addr, phy_page = 0;
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- ret_val = hw->phy.ops.acquire_phy(hw);
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+ ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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return ret_val;
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@@ -912,7 +912,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
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reg_addr &= PHY_REG_MASK;
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reg_addr |= phy_page;
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- ret_val = phy->ops.write_phy_reg_locked(hw,
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+ ret_val = phy->ops.write_reg_locked(hw,
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(u32)reg_addr,
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reg_data);
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if (ret_val)
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@@ -921,7 +921,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
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}
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out:
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- hw->phy.ops.release_phy(hw);
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+ hw->phy.ops.release(hw);
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return ret_val;
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}
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@@ -945,15 +945,14 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
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goto out;
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/* Wrap the whole flow with the sw flag */
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- ret_val = hw->phy.ops.acquire_phy(hw);
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+ ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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goto out;
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/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
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if (link) {
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if (hw->phy.type == e1000_phy_82578) {
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- ret_val = hw->phy.ops.read_phy_reg_locked(hw,
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- BM_CS_STATUS,
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+ ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
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&status_reg);
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if (ret_val)
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goto release;
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@@ -969,8 +968,7 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
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}
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if (hw->phy.type == e1000_phy_82577) {
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- ret_val = hw->phy.ops.read_phy_reg_locked(hw,
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- HV_M_STATUS,
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+ ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
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&status_reg);
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if (ret_val)
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goto release;
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@@ -986,14 +984,14 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
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}
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/* Link stall fix for link up */
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- ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
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+ ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
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0x0100);
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if (ret_val)
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goto release;
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} else {
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/* Link stall fix for link down */
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- ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
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+ ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
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0x4100);
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if (ret_val)
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goto release;
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@@ -1002,7 +1000,7 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
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ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
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release:
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- hw->phy.ops.release_phy(hw);
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+ hw->phy.ops.release(hw);
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out:
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return ret_val;
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}
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@@ -1078,7 +1076,7 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
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if (hw->mac.type != e1000_pchlan)
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return ret_val;
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- ret_val = hw->phy.ops.acquire_phy(hw);
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+ ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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return ret_val;
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@@ -1092,7 +1090,7 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
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mac_reg = er32(PHY_CTRL);
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- ret_val = hw->phy.ops.read_phy_reg_locked(hw, HV_OEM_BITS, &oem_reg);
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+ ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
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if (ret_val)
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goto out;
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@@ -1113,10 +1111,10 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
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}
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/* Restart auto-neg to activate the bits */
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oem_reg |= HV_OEM_BITS_RESTART_AN;
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- ret_val = hw->phy.ops.write_phy_reg_locked(hw, HV_OEM_BITS, oem_reg);
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+ ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
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out:
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- hw->phy.ops.release_phy(hw);
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+ hw->phy.ops.release(hw);
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return ret_val;
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}
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@@ -1159,7 +1157,7 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
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}
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/* Select page 0 */
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- ret_val = hw->phy.ops.acquire_phy(hw);
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+ ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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return ret_val;
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@@ -1167,7 +1165,7 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
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ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
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if (ret_val)
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goto out;
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- hw->phy.ops.release_phy(hw);
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+ hw->phy.ops.release(hw);
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/*
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* Configure the K1 Si workaround during phy reset assuming there is
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@@ -1667,7 +1665,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
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goto out;
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}
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- nvm->ops.acquire_nvm(hw);
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+ nvm->ops.acquire(hw);
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ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
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if (ret_val) {
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@@ -1693,7 +1691,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
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}
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}
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- nvm->ops.release_nvm(hw);
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+ nvm->ops.release(hw);
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out:
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if (ret_val)
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@@ -1951,14 +1949,14 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
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return -E1000_ERR_NVM;
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}
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- nvm->ops.acquire_nvm(hw);
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+ nvm->ops.acquire(hw);
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for (i = 0; i < words; i++) {
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dev_spec->shadow_ram[offset+i].modified = 1;
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dev_spec->shadow_ram[offset+i].value = data[i];
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}
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- nvm->ops.release_nvm(hw);
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+ nvm->ops.release(hw);
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return 0;
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}
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@@ -1989,7 +1987,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
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if (nvm->type != e1000_nvm_flash_sw)
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goto out;
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- nvm->ops.acquire_nvm(hw);
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+ nvm->ops.acquire(hw);
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/*
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* We're writing to the opposite bank so if we're on bank 1,
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@@ -2007,7 +2005,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
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old_bank_offset = 0;
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ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
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if (ret_val) {
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- nvm->ops.release_nvm(hw);
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+ nvm->ops.release(hw);
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goto out;
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}
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} else {
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@@ -2015,7 +2013,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
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new_bank_offset = 0;
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ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
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if (ret_val) {
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- nvm->ops.release_nvm(hw);
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+ nvm->ops.release(hw);
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goto out;
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}
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}
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@@ -2073,7 +2071,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
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if (ret_val) {
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/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
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e_dbg("Flash commit failed.\n");
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- nvm->ops.release_nvm(hw);
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+ nvm->ops.release(hw);
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goto out;
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}
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@@ -2086,7 +2084,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
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act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
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ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
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if (ret_val) {
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- nvm->ops.release_nvm(hw);
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+ nvm->ops.release(hw);
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goto out;
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}
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data &= 0xBFFF;
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@@ -2094,7 +2092,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
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act_offset * 2 + 1,
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(u8)(data >> 8));
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if (ret_val) {
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- nvm->ops.release_nvm(hw);
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+ nvm->ops.release(hw);
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goto out;
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}
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@@ -2107,7 +2105,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
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act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
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ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
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if (ret_val) {
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- nvm->ops.release_nvm(hw);
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+ nvm->ops.release(hw);
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goto out;
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}
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@@ -2117,7 +2115,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
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dev_spec->shadow_ram[i].value = 0xFFFF;
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}
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- nvm->ops.release_nvm(hw);
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+ nvm->ops.release(hw);
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/*
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* Reload the EEPROM, or else modifications will not appear
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@@ -2186,7 +2184,7 @@ void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
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union ich8_hws_flash_status hsfsts;
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u32 gfpreg;
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- nvm->ops.acquire_nvm(hw);
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+ nvm->ops.acquire(hw);
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gfpreg = er32flash(ICH_FLASH_GFPREG);
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@@ -2207,7 +2205,7 @@ void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
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hsfsts.hsf_status.flockdn = true;
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ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
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- nvm->ops.release_nvm(hw);
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+ nvm->ops.release(hw);
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}
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/**
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@@ -2743,7 +2741,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
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* Reset the phy after disabling host wakeup to reset the Rx buffer.
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*/
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if (hw->phy.type == e1000_phy_82578) {
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- hw->phy.ops.read_phy_reg(hw, BM_WUC, &i);
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+ hw->phy.ops.read_reg(hw, BM_WUC, &i);
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ret_val = e1000_phy_hw_reset_ich8lan(hw);
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if (ret_val)
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return ret_val;
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@@ -2890,7 +2888,7 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
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ew32(FCTTV, hw->fc.pause_time);
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if ((hw->phy.type == e1000_phy_82578) ||
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(hw->phy.type == e1000_phy_82577)) {
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- ret_val = hw->phy.ops.write_phy_reg(hw,
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+ ret_val = hw->phy.ops.write_reg(hw,
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PHY_REG(BM_PORT_CTRL_PAGE, 27),
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hw->fc.pause_time);
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if (ret_val)
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@@ -2953,7 +2951,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
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return ret_val;
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break;
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case e1000_phy_ife:
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- ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
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+ ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
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®_data);
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if (ret_val)
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return ret_val;
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@@ -2972,7 +2970,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
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reg_data |= IFE_PMC_AUTO_MDIX;
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break;
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}
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- ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
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+ ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
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reg_data);
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if (ret_val)
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return ret_val;
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@@ -3274,7 +3272,7 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
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**/
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static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
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{
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- return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
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+ return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
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(u16)hw->mac.ledctl_mode1);
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}
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@@ -3286,7 +3284,7 @@ static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
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**/
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static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
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{
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- return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
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+ return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
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(u16)hw->mac.ledctl_default);
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}
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@@ -3318,7 +3316,7 @@ static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
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}
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}
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- return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
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+ return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
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}
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/**
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@@ -3349,7 +3347,7 @@ static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
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}
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}
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- return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
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+ return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
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}
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/**
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@@ -3426,20 +3424,20 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
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/* Clear PHY statistics registers */
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if ((hw->phy.type == e1000_phy_82578) ||
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(hw->phy.type == e1000_phy_82577)) {
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- hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
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- hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
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- hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
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- hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
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- hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
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- hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
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- hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
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- hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
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- hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
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- hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
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- hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data);
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- hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data);
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- hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
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- hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
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+ hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
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+ hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
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+ hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
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+ hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
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+ hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
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+ hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
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+ hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
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+ hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
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+ hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
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+ hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
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+ hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
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+ hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
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+ hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
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+ hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
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|
|
}
|
|
|
}
|
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|
|
@@ -3462,29 +3460,29 @@ static struct e1000_mac_operations ich8_mac_ops = {
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|
|
};
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|
|
|
static struct e1000_phy_operations ich8_phy_ops = {
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|
|
- .acquire_phy = e1000_acquire_swflag_ich8lan,
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|
+ .acquire = e1000_acquire_swflag_ich8lan,
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|
|
.check_reset_block = e1000_check_reset_block_ich8lan,
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|
|
- .commit_phy = NULL,
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|
+ .commit = NULL,
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|
|
.force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
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|
|
.get_cfg_done = e1000_get_cfg_done_ich8lan,
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|
|
.get_cable_length = e1000e_get_cable_length_igp_2,
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|
|
- .get_phy_info = e1000_get_phy_info_ich8lan,
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|
|
- .read_phy_reg = e1000e_read_phy_reg_igp,
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|
|
- .release_phy = e1000_release_swflag_ich8lan,
|
|
|
- .reset_phy = e1000_phy_hw_reset_ich8lan,
|
|
|
+ .get_info = e1000_get_phy_info_ich8lan,
|
|
|
+ .read_reg = e1000e_read_phy_reg_igp,
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|
|
+ .release = e1000_release_swflag_ich8lan,
|
|
|
+ .reset = e1000_phy_hw_reset_ich8lan,
|
|
|
.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
|
|
|
.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
|
|
|
- .write_phy_reg = e1000e_write_phy_reg_igp,
|
|
|
+ .write_reg = e1000e_write_phy_reg_igp,
|
|
|
};
|
|
|
|
|
|
static struct e1000_nvm_operations ich8_nvm_ops = {
|
|
|
- .acquire_nvm = e1000_acquire_nvm_ich8lan,
|
|
|
- .read_nvm = e1000_read_nvm_ich8lan,
|
|
|
- .release_nvm = e1000_release_nvm_ich8lan,
|
|
|
- .update_nvm = e1000_update_nvm_checksum_ich8lan,
|
|
|
+ .acquire = e1000_acquire_nvm_ich8lan,
|
|
|
+ .read = e1000_read_nvm_ich8lan,
|
|
|
+ .release = e1000_release_nvm_ich8lan,
|
|
|
+ .update = e1000_update_nvm_checksum_ich8lan,
|
|
|
.valid_led_default = e1000_valid_led_default_ich8lan,
|
|
|
- .validate_nvm = e1000_validate_nvm_checksum_ich8lan,
|
|
|
- .write_nvm = e1000_write_nvm_ich8lan,
|
|
|
+ .validate = e1000_validate_nvm_checksum_ich8lan,
|
|
|
+ .write = e1000_write_nvm_ich8lan,
|
|
|
};
|
|
|
|
|
|
struct e1000_info e1000_ich8_info = {
|