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@@ -33,6 +33,7 @@
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#include <asm/msr.h>
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#include <asm/proto.h>
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#include <asm/kdebug.h>
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+#include <asm/local.h>
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/*
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* lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
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@@ -59,7 +60,8 @@ int panic_on_timeout;
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unsigned int nmi_watchdog = NMI_DEFAULT;
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static unsigned int nmi_hz = HZ;
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-unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
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+static unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
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+static unsigned int nmi_p4_cccr_val;
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/* Note that these events don't tick when the CPU idles. This means
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the frequency varies with CPU load. */
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@@ -71,61 +73,87 @@ unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
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#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
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#define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
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-#define P6_EVNTSEL0_ENABLE (1 << 22)
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-#define P6_EVNTSEL_INT (1 << 20)
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-#define P6_EVNTSEL_OS (1 << 17)
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-#define P6_EVNTSEL_USR (1 << 16)
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-#define P6_EVENT_CPU_CLOCKS_NOT_HALTED 0x79
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-#define P6_NMI_EVENT P6_EVENT_CPU_CLOCKS_NOT_HALTED
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+#define MSR_P4_MISC_ENABLE 0x1A0
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+#define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
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+#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
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+#define MSR_P4_PERFCTR0 0x300
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+#define MSR_P4_CCCR0 0x360
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+#define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
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+#define P4_ESCR_OS (1<<3)
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+#define P4_ESCR_USR (1<<2)
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+#define P4_CCCR_OVF_PMI0 (1<<26)
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+#define P4_CCCR_OVF_PMI1 (1<<27)
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+#define P4_CCCR_THRESHOLD(N) ((N)<<20)
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+#define P4_CCCR_COMPLEMENT (1<<19)
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+#define P4_CCCR_COMPARE (1<<18)
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+#define P4_CCCR_REQUIRED (3<<16)
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+#define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
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+#define P4_CCCR_ENABLE (1<<12)
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+/* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
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+ CRU_ESCR0 (with any non-null event selector) through a complemented
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+ max threshold. [IA32-Vol3, Section 14.9.9] */
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+#define MSR_P4_IQ_COUNTER0 0x30C
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+#define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
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+#define P4_NMI_IQ_CCCR0 \
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+ (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
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+ P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
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+
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+static __init inline int nmi_known_cpu(void)
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+{
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+ switch (boot_cpu_data.x86_vendor) {
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+ case X86_VENDOR_AMD:
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+ return boot_cpu_data.x86 == 15;
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+ case X86_VENDOR_INTEL:
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+ return boot_cpu_data.x86 == 15;
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+ }
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+ return 0;
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+}
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/* Run after command line and cpu_init init, but before all other checks */
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void __init nmi_watchdog_default(void)
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{
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if (nmi_watchdog != NMI_DEFAULT)
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return;
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-
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- /* For some reason the IO APIC watchdog doesn't work on the AMD
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- 8111 chipset. For now switch to local APIC mode using
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- perfctr0 there. On Intel CPUs we don't have code to handle
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- the perfctr and the IO-APIC seems to work, so use that. */
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-
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- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
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- nmi_watchdog = NMI_LOCAL_APIC;
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- printk(KERN_INFO
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- "Using local APIC NMI watchdog using perfctr0\n");
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- } else {
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- printk(KERN_INFO "Using IO APIC NMI watchdog\n");
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+ if (nmi_known_cpu())
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+ nmi_watchdog = NMI_LOCAL_APIC;
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+ else
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nmi_watchdog = NMI_IO_APIC;
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- }
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}
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-/* Why is there no CPUID flag for this? */
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-static __init int cpu_has_lapic(void)
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+#ifdef CONFIG_SMP
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+/* The performance counters used by NMI_LOCAL_APIC don't trigger when
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+ * the CPU is idle. To make sure the NMI watchdog really ticks on all
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+ * CPUs during the test make them busy.
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+ */
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+static __init void nmi_cpu_busy(void *data)
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{
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- switch (boot_cpu_data.x86_vendor) {
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- case X86_VENDOR_INTEL:
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- case X86_VENDOR_AMD:
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- return boot_cpu_data.x86 >= 6;
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- /* .... add more cpus here or find a different way to figure this out. */
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- default:
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- return 0;
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- }
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+ volatile int *endflag = data;
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+ local_irq_enable();
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+ /* Intentionally don't use cpu_relax here. This is
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+ to make sure that the performance counter really ticks,
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+ even if there is a simulator or similar that catches the
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+ pause instruction. On a real HT machine this is fine because
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+ all other CPUs are busy with "useless" delay loops and don't
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+ care if they get somewhat less cycles. */
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+ while (*endflag == 0)
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+ barrier();
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}
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+#endif
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-static int __init check_nmi_watchdog (void)
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+int __init check_nmi_watchdog (void)
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{
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- int counts[NR_CPUS];
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+ volatile int endflag = 0;
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+ int *counts;
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int cpu;
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- if (nmi_watchdog == NMI_NONE)
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- return 0;
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+ counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
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+ if (!counts)
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+ return -1;
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- if (nmi_watchdog == NMI_LOCAL_APIC && !cpu_has_lapic()) {
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- nmi_watchdog = NMI_NONE;
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- return -1;
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- }
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+ printk(KERN_INFO "testing NMI watchdog ... ");
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- printk(KERN_INFO "Testing NMI watchdog ... ");
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+ if (nmi_watchdog == NMI_LOCAL_APIC)
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+ smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
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for (cpu = 0; cpu < NR_CPUS; cpu++)
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counts[cpu] = cpu_pda[cpu].__nmi_count;
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@@ -133,15 +161,22 @@ static int __init check_nmi_watchdog (void)
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mdelay((10*1000)/nmi_hz); // wait 10 ticks
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for (cpu = 0; cpu < NR_CPUS; cpu++) {
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+ if (!cpu_online(cpu))
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+ continue;
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if (cpu_pda[cpu].__nmi_count - counts[cpu] <= 5) {
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- printk("CPU#%d: NMI appears to be stuck (%d)!\n",
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+ endflag = 1;
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+ printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
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cpu,
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+ counts[cpu],
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cpu_pda[cpu].__nmi_count);
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nmi_active = 0;
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lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
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+ nmi_perfctr_msr = 0;
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+ kfree(counts);
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return -1;
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}
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}
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+ endflag = 1;
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printk("OK.\n");
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/* now that we know it works we can reduce NMI frequency to
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@@ -149,10 +184,9 @@ static int __init check_nmi_watchdog (void)
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if (nmi_watchdog == NMI_LOCAL_APIC)
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nmi_hz = 1;
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+ kfree(counts);
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return 0;
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}
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-/* Have this called later during boot so counters are updating */
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-late_initcall(check_nmi_watchdog);
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int __init setup_nmi_watchdog(char *str)
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{
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@@ -170,7 +204,7 @@ int __init setup_nmi_watchdog(char *str)
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if (nmi >= NMI_INVALID)
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return 0;
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- nmi_watchdog = nmi;
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+ nmi_watchdog = nmi;
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return 1;
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}
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@@ -185,7 +219,10 @@ static void disable_lapic_nmi_watchdog(void)
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wrmsr(MSR_K7_EVNTSEL0, 0, 0);
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break;
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case X86_VENDOR_INTEL:
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- wrmsr(MSR_IA32_EVNTSEL0, 0, 0);
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+ if (boot_cpu_data.x86 == 15) {
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+ wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
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+ wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
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+ }
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break;
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}
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nmi_active = -1;
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@@ -253,7 +290,7 @@ void enable_timer_nmi_watchdog(void)
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static int nmi_pm_active; /* nmi_active before suspend */
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-static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
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+static int lapic_nmi_suspend(struct sys_device *dev, u32 state)
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{
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nmi_pm_active = nmi_active;
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disable_lapic_nmi_watchdog();
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@@ -300,22 +337,27 @@ late_initcall(init_lapic_nmi_sysfs);
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* Original code written by Keith Owens.
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*/
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+static void clear_msr_range(unsigned int base, unsigned int n)
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+{
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+ unsigned int i;
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+
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+ for(i = 0; i < n; ++i)
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+ wrmsr(base+i, 0, 0);
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+}
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+
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static void setup_k7_watchdog(void)
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{
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int i;
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unsigned int evntsel;
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- /* No check, so can start with slow frequency */
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- nmi_hz = 1;
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-
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- /* XXX should check these in EFER */
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-
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nmi_perfctr_msr = MSR_K7_PERFCTR0;
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for(i = 0; i < 4; ++i) {
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/* Simulator may not support it */
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- if (checking_wrmsrl(MSR_K7_EVNTSEL0+i, 0UL))
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+ if (checking_wrmsrl(MSR_K7_EVNTSEL0+i, 0UL)) {
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+ nmi_perfctr_msr = 0;
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return;
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+ }
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wrmsrl(MSR_K7_PERFCTR0+i, 0UL);
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}
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@@ -325,12 +367,54 @@ static void setup_k7_watchdog(void)
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| K7_NMI_EVENT;
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wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
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- wrmsrl(MSR_K7_PERFCTR0, -((u64)cpu_khz*1000) / nmi_hz);
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+ wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1);
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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evntsel |= K7_EVNTSEL_ENABLE;
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wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
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}
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+
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+static int setup_p4_watchdog(void)
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+{
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+ unsigned int misc_enable, dummy;
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+
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+ rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
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+ if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
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+ return 0;
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+
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+ nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
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+ nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
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+#ifdef CONFIG_SMP
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+ if (smp_num_siblings == 2)
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+ nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
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+#endif
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+
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+ if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
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+ clear_msr_range(0x3F1, 2);
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+ /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
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+ docs doesn't fully define it, so leave it alone for now. */
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+ if (boot_cpu_data.x86_model >= 0x3) {
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+ /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
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+ clear_msr_range(0x3A0, 26);
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+ clear_msr_range(0x3BC, 3);
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+ } else {
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+ clear_msr_range(0x3A0, 31);
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+ }
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+ clear_msr_range(0x3C0, 6);
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+ clear_msr_range(0x3C8, 6);
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+ clear_msr_range(0x3E0, 2);
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+ clear_msr_range(MSR_P4_CCCR0, 18);
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+ clear_msr_range(MSR_P4_PERFCTR0, 18);
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+
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+ wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
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+ wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
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+ Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
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+ wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);
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+ apic_write(APIC_LVTPC, APIC_DM_NMI);
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+ wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
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+ return 1;
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+}
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+
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void setup_apic_nmi_watchdog(void)
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{
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switch (boot_cpu_data.x86_vendor) {
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@@ -341,6 +425,13 @@ void setup_apic_nmi_watchdog(void)
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return;
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setup_k7_watchdog();
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break;
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+ case X86_VENDOR_INTEL:
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+ if (boot_cpu_data.x86 != 15)
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+ return;
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+ if (!setup_p4_watchdog())
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+ return;
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+ break;
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+
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default:
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return;
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}
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@@ -355,56 +446,67 @@ void setup_apic_nmi_watchdog(void)
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*
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* as these watchdog NMI IRQs are generated on every CPU, we only
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* have to check the current processor.
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- *
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- * since NMIs don't listen to _any_ locks, we have to be extremely
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- * careful not to rely on unsafe variables. The printk might lock
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- * up though, so we have to break up any console locks first ...
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- * [when there will be more tty-related locks, break them up
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- * here too!]
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*/
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-static unsigned int
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- last_irq_sums [NR_CPUS],
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- alert_counter [NR_CPUS];
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+static DEFINE_PER_CPU(unsigned, last_irq_sum);
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+static DEFINE_PER_CPU(local_t, alert_counter);
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+static DEFINE_PER_CPU(int, nmi_touch);
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void touch_nmi_watchdog (void)
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{
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int i;
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/*
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- * Just reset the alert counters, (other CPUs might be
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- * spinning on locks we hold):
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+ * Tell other CPUs to reset their alert counters. We cannot
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+ * do it ourselves because the alert count increase is not
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+ * atomic.
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*/
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for (i = 0; i < NR_CPUS; i++)
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- alert_counter[i] = 0;
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+ per_cpu(nmi_touch, i) = 1;
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}
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void nmi_watchdog_tick (struct pt_regs * regs, unsigned reason)
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{
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- int sum, cpu;
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+ int sum;
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+ int touched = 0;
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- cpu = safe_smp_processor_id();
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sum = read_pda(apic_timer_irqs);
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- if (last_irq_sums[cpu] == sum) {
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+ if (__get_cpu_var(nmi_touch)) {
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+ __get_cpu_var(nmi_touch) = 0;
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+ touched = 1;
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+ }
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+ if (!touched && __get_cpu_var(last_irq_sum) == sum) {
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/*
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* Ayiee, looks like this CPU is stuck ...
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* wait a few IRQs (5 seconds) before doing the oops ...
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*/
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- alert_counter[cpu]++;
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- if (alert_counter[cpu] == 5*nmi_hz) {
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+ local_inc(&__get_cpu_var(alert_counter));
|
|
|
+ if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz) {
|
|
|
if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
|
|
|
== NOTIFY_STOP) {
|
|
|
- alert_counter[cpu] = 0;
|
|
|
+ local_set(&__get_cpu_var(alert_counter), 0);
|
|
|
return;
|
|
|
}
|
|
|
die_nmi("NMI Watchdog detected LOCKUP on CPU%d", regs);
|
|
|
}
|
|
|
} else {
|
|
|
- last_irq_sums[cpu] = sum;
|
|
|
- alert_counter[cpu] = 0;
|
|
|
+ __get_cpu_var(last_irq_sum) = sum;
|
|
|
+ local_set(&__get_cpu_var(alert_counter), 0);
|
|
|
}
|
|
|
- if (nmi_perfctr_msr)
|
|
|
+ if (nmi_perfctr_msr) {
|
|
|
+ if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
|
|
|
+ /*
|
|
|
+ * P4 quirks:
|
|
|
+ * - An overflown perfctr will assert its interrupt
|
|
|
+ * until the OVF flag in its CCCR is cleared.
|
|
|
+ * - LVTPC is masked on interrupt and must be
|
|
|
+ * unmasked by the LVTPC handler.
|
|
|
+ */
|
|
|
+ wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
|
|
|
+ apic_write(APIC_LVTPC, APIC_DM_NMI);
|
|
|
+ }
|
|
|
wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1);
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
static int dummy_nmi_callback(struct pt_regs * regs, int cpu)
|