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@@ -195,10 +195,10 @@ struct x86_pmu {
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u64 (*event_map)(int);
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u64 (*raw_event)(u64);
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int max_events;
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- int num_events;
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- int num_events_fixed;
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- int event_bits;
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- u64 event_mask;
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+ int num_counters;
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+ int num_counters_fixed;
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+ int cntval_bits;
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+ u64 cntval_mask;
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int apic;
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u64 max_period;
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struct event_constraint *
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@@ -268,7 +268,7 @@ static u64
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x86_perf_event_update(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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- int shift = 64 - x86_pmu.event_bits;
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+ int shift = 64 - x86_pmu.cntval_bits;
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u64 prev_raw_count, new_raw_count;
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int idx = hwc->idx;
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s64 delta;
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@@ -320,12 +320,12 @@ static bool reserve_pmc_hardware(void)
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if (nmi_watchdog == NMI_LOCAL_APIC)
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disable_lapic_nmi_watchdog();
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- for (i = 0; i < x86_pmu.num_events; i++) {
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+ for (i = 0; i < x86_pmu.num_counters; i++) {
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if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
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goto perfctr_fail;
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}
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- for (i = 0; i < x86_pmu.num_events; i++) {
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+ for (i = 0; i < x86_pmu.num_counters; i++) {
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if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
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goto eventsel_fail;
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}
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@@ -336,7 +336,7 @@ eventsel_fail:
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for (i--; i >= 0; i--)
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release_evntsel_nmi(x86_pmu.eventsel + i);
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- i = x86_pmu.num_events;
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+ i = x86_pmu.num_counters;
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perfctr_fail:
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for (i--; i >= 0; i--)
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@@ -352,7 +352,7 @@ static void release_pmc_hardware(void)
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{
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int i;
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- for (i = 0; i < x86_pmu.num_events; i++) {
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+ for (i = 0; i < x86_pmu.num_counters; i++) {
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release_perfctr_nmi(x86_pmu.perfctr + i);
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release_evntsel_nmi(x86_pmu.eventsel + i);
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}
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@@ -547,7 +547,7 @@ static void x86_pmu_disable_all(void)
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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int idx;
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- for (idx = 0; idx < x86_pmu.num_events; idx++) {
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+ for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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u64 val;
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if (!test_bit(idx, cpuc->active_mask))
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@@ -582,7 +582,7 @@ static void x86_pmu_enable_all(int added)
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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int idx;
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- for (idx = 0; idx < x86_pmu.num_events; idx++) {
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+ for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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struct perf_event *event = cpuc->events[idx];
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u64 val;
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@@ -657,14 +657,14 @@ static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
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* assign events to counters starting with most
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* constrained events.
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*/
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- wmax = x86_pmu.num_events;
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+ wmax = x86_pmu.num_counters;
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/*
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* when fixed event counters are present,
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* wmax is incremented by 1 to account
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* for one more choice
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*/
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- if (x86_pmu.num_events_fixed)
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+ if (x86_pmu.num_counters_fixed)
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wmax++;
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for (w = 1, num = n; num && w <= wmax; w++) {
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@@ -714,7 +714,7 @@ static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader,
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struct perf_event *event;
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int n, max_count;
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- max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
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+ max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
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/* current number of events already accepted */
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n = cpuc->n_events;
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@@ -904,7 +904,7 @@ x86_perf_event_set_period(struct perf_event *event)
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atomic64_set(&hwc->prev_count, (u64)-left);
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wrmsrl(hwc->event_base + idx,
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- (u64)(-left) & x86_pmu.event_mask);
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+ (u64)(-left) & x86_pmu.cntval_mask);
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perf_event_update_userpage(event);
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@@ -987,7 +987,7 @@ void perf_event_print_debug(void)
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unsigned long flags;
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int cpu, idx;
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- if (!x86_pmu.num_events)
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+ if (!x86_pmu.num_counters)
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return;
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local_irq_save(flags);
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@@ -1011,7 +1011,7 @@ void perf_event_print_debug(void)
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}
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pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
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- for (idx = 0; idx < x86_pmu.num_events; idx++) {
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+ for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
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rdmsrl(x86_pmu.perfctr + idx, pmc_count);
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@@ -1024,7 +1024,7 @@ void perf_event_print_debug(void)
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pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
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cpu, idx, prev_left);
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}
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- for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
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+ for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
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rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
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pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
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@@ -1089,7 +1089,7 @@ static int x86_pmu_handle_irq(struct pt_regs *regs)
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cpuc = &__get_cpu_var(cpu_hw_events);
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- for (idx = 0; idx < x86_pmu.num_events; idx++) {
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+ for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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if (!test_bit(idx, cpuc->active_mask))
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continue;
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@@ -1097,7 +1097,7 @@ static int x86_pmu_handle_irq(struct pt_regs *regs)
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hwc = &event->hw;
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val = x86_perf_event_update(event);
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- if (val & (1ULL << (x86_pmu.event_bits - 1)))
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+ if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
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continue;
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/*
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@@ -1401,46 +1401,46 @@ void __init init_hw_perf_events(void)
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if (x86_pmu.quirks)
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x86_pmu.quirks();
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- if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
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+ if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
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WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
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- x86_pmu.num_events, X86_PMC_MAX_GENERIC);
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- x86_pmu.num_events = X86_PMC_MAX_GENERIC;
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+ x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
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+ x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
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}
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- x86_pmu.intel_ctrl = (1 << x86_pmu.num_events) - 1;
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- perf_max_events = x86_pmu.num_events;
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+ x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
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+ perf_max_events = x86_pmu.num_counters;
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- if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
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+ if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
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WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
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- x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
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- x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
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+ x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
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+ x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
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}
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x86_pmu.intel_ctrl |=
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- ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
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+ ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
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perf_events_lapic_init();
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register_die_notifier(&perf_event_nmi_notifier);
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unconstrained = (struct event_constraint)
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- __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1,
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- 0, x86_pmu.num_events);
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+ __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
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+ 0, x86_pmu.num_counters);
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if (x86_pmu.event_constraints) {
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for_each_event_constraint(c, x86_pmu.event_constraints) {
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if (c->cmask != INTEL_ARCH_FIXED_MASK)
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continue;
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- c->idxmsk64 |= (1ULL << x86_pmu.num_events) - 1;
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- c->weight += x86_pmu.num_events;
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+ c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
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+ c->weight += x86_pmu.num_counters;
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}
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}
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pr_info("... version: %d\n", x86_pmu.version);
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- pr_info("... bit width: %d\n", x86_pmu.event_bits);
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- pr_info("... generic registers: %d\n", x86_pmu.num_events);
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- pr_info("... value mask: %016Lx\n", x86_pmu.event_mask);
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+ pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
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+ pr_info("... generic registers: %d\n", x86_pmu.num_counters);
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+ pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
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pr_info("... max period: %016Lx\n", x86_pmu.max_period);
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- pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed);
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+ pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
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pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
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perf_cpu_notifier(x86_pmu_notifier);
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