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@@ -740,9 +740,9 @@ static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
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* (translation) interrupts.
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*/
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spin_lock_irq(&spu->register_lock);
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- spu_int_stat_clear(spu, 0, ~0ul);
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- spu_int_stat_clear(spu, 1, ~0ul);
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- spu_int_stat_clear(spu, 2, ~0ul);
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+ spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
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+ spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
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+ spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
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spu_int_mask_set(spu, 0, 0ul);
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spu_int_mask_set(spu, 1, class1_mask);
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spu_int_mask_set(spu, 2, 0ul);
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@@ -899,8 +899,8 @@ static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
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POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
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local_irq_save(flags);
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- spu_int_stat_clear(spu, 0, ~(0ul));
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- spu_int_stat_clear(spu, 2, ~(0ul));
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+ spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
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+ spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
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local_irq_restore(flags);
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}
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@@ -918,8 +918,8 @@ static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
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POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
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local_irq_save(flags);
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- spu_int_stat_clear(spu, 0, ~(0ul));
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- spu_int_stat_clear(spu, 2, ~(0ul));
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+ spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
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+ spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
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local_irq_restore(flags);
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}
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@@ -1395,9 +1395,9 @@ static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
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spu_int_mask_set(spu, 0, 0ul);
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spu_int_mask_set(spu, 1, 0ul);
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spu_int_mask_set(spu, 2, 0ul);
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- spu_int_stat_clear(spu, 0, ~0ul);
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- spu_int_stat_clear(spu, 1, ~0ul);
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- spu_int_stat_clear(spu, 2, ~0ul);
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+ spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
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+ spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
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+ spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
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spin_unlock_irq(&spu->register_lock);
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}
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