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@@ -97,6 +97,7 @@ enum {
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REPLY_ADD_STA = 0x18,
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REPLY_ADD_STA = 0x18,
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REPLY_REMOVE_STA = 0x19,
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REPLY_REMOVE_STA = 0x19,
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REPLY_REMOVE_ALL_STA = 0x1a, /* not used */
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REPLY_REMOVE_ALL_STA = 0x1a, /* not used */
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+ REPLY_TXFIFO_FLUSH = 0x1e,
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/* Security */
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/* Security */
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REPLY_WEPKEY = 0x20,
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REPLY_WEPKEY = 0x20,
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@@ -1209,6 +1210,39 @@ struct iwl_rem_sta_cmd {
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u8 reserved2[2];
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u8 reserved2[2];
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} __attribute__ ((packed));
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} __attribute__ ((packed));
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+#define IWL_TX_FIFO_BK_MSK cpu_to_le32(BIT(0))
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+#define IWL_TX_FIFO_BE_MSK cpu_to_le32(BIT(1))
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+#define IWL_TX_FIFO_VI_MSK cpu_to_le32(BIT(2))
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+#define IWL_TX_FIFO_VO_MSK cpu_to_le32(BIT(3))
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+#define IWL_AGG_TX_QUEUE_MSK cpu_to_le32(0xffc00)
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+
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+/*
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+ * REPLY_TXFIFO_FLUSH = 0x1e(command and response)
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+ *
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+ * When using full FIFO flush this command checks the scheduler HW block WR/RD
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+ * pointers to check if all the frames were transferred by DMA into the
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+ * relevant TX FIFO queue. Only when the DMA is finished and the queue is
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+ * empty the command can finish.
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+ * This command is used to flush the TXFIFO from transmit commands, it may
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+ * operate on single or multiple queues, the command queue can't be flushed by
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+ * this command. The command response is returned when all the queue flush
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+ * operations are done. Each TX command flushed return response with the FLUSH
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+ * status set in the TX response status. When FIFO flush operation is used,
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+ * the flush operation ends when both the scheduler DMA done and TXFIFO empty
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+ * are set.
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+ *
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+ * @fifo_control: bit mask for which queues to flush
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+ * @flush_control: flush controls
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+ * 0: Dump single MSDU
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+ * 1: Dump multiple MSDU according to PS, INVALID STA, TTL, TID disable.
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+ * 2: Dump all FIFO
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+ */
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+struct iwl_txfifo_flush_cmd {
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+ __le32 fifo_control;
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+ __le16 flush_control;
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+ __le16 reserved;
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+} __attribute__ ((packed));
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+
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/*
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/*
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* REPLY_WEP_KEY = 0x20
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* REPLY_WEP_KEY = 0x20
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*/
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*/
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