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@@ -155,43 +155,43 @@ static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
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32 - ffs(mask)));
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}
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-static void mpc8xxx_irq_unmask(unsigned int virq)
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+static void mpc8xxx_irq_unmask(struct irq_data *d)
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{
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- struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
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+ struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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- setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq)));
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+ setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(d->irq)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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-static void mpc8xxx_irq_mask(unsigned int virq)
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+static void mpc8xxx_irq_mask(struct irq_data *d)
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{
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- struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
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+ struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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- clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq)));
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+ clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(d->irq)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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-static void mpc8xxx_irq_ack(unsigned int virq)
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+static void mpc8xxx_irq_ack(struct irq_data *d)
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{
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- struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
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+ struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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- out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(virq_to_hw(virq)));
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+ out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(virq_to_hw(d->irq)));
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}
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-static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type)
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+static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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- struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
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+ struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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@@ -199,14 +199,14 @@ static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type)
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case IRQ_TYPE_EDGE_FALLING:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_ICR,
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- mpc8xxx_gpio2mask(virq_to_hw(virq)));
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+ mpc8xxx_gpio2mask(virq_to_hw(d->irq)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_ICR,
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- mpc8xxx_gpio2mask(virq_to_hw(virq)));
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+ mpc8xxx_gpio2mask(virq_to_hw(d->irq)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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@@ -217,11 +217,11 @@ static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type)
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return 0;
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}
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-static int mpc512x_irq_set_type(unsigned int virq, unsigned int flow_type)
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+static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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- struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
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+ struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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- unsigned long gpio = virq_to_hw(virq);
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+ unsigned long gpio = virq_to_hw(d->irq);
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void __iomem *reg;
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unsigned int shift;
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unsigned long flags;
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@@ -264,10 +264,10 @@ static int mpc512x_irq_set_type(unsigned int virq, unsigned int flow_type)
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static struct irq_chip mpc8xxx_irq_chip = {
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.name = "mpc8xxx-gpio",
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- .unmask = mpc8xxx_irq_unmask,
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- .mask = mpc8xxx_irq_mask,
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- .ack = mpc8xxx_irq_ack,
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- .set_type = mpc8xxx_irq_set_type,
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+ .irq_unmask = mpc8xxx_irq_unmask,
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+ .irq_mask = mpc8xxx_irq_mask,
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+ .irq_ack = mpc8xxx_irq_ack,
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+ .irq_set_type = mpc8xxx_irq_set_type,
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};
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static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
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@@ -276,7 +276,7 @@ static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
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if (mpc8xxx_gc->of_dev_id_data)
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- mpc8xxx_irq_chip.set_type = mpc8xxx_gc->of_dev_id_data;
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+ mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
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set_irq_chip_data(virq, h->host_data);
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set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
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