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@@ -1832,12 +1832,16 @@ void intel_flush_display_plane(struct drm_i915_private *dev_priv,
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static void intel_enable_plane(struct drm_i915_private *dev_priv,
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enum plane plane, enum pipe pipe)
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{
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+ struct intel_crtc *intel_crtc =
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+ to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
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int reg;
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u32 val;
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/* If the pipe isn't enabled, we can't pump pixels and may hang */
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assert_pipe_enabled(dev_priv, pipe);
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+ intel_crtc->primary_disabled = false;
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+
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reg = DSPCNTR(plane);
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val = I915_READ(reg);
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if (val & DISPLAY_PLANE_ENABLE)
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@@ -1859,9 +1863,13 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv,
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static void intel_disable_plane(struct drm_i915_private *dev_priv,
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enum plane plane, enum pipe pipe)
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{
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+ struct intel_crtc *intel_crtc =
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+ to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
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int reg;
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u32 val;
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+ intel_crtc->primary_disabled = true;
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+
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reg = DSPCNTR(plane);
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val = I915_READ(reg);
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if ((val & DISPLAY_PLANE_ENABLE) == 0)
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