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@@ -1766,12 +1766,11 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
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/*
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* TX descriptor initialization
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*/
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-static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
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- struct sk_buff *skb,
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+static void rt61pci_write_tx_desc(struct queue_entry *entry,
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struct txentry_desc *txdesc)
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{
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- struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
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- struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
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+ struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
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+ struct queue_entry_priv_pci *entry_priv = entry->priv_data;
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__le32 *txd = entry_priv->desc;
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u32 word;
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@@ -1802,11 +1801,11 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
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}
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rt2x00_desc_read(txd, 5, &word);
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- rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
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+ rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
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rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
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skbdesc->entry->entry_idx);
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rt2x00_set_field32(&word, TXD_W5_TX_POWER,
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- TXPOWER_TO_DEV(rt2x00dev->tx_power));
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+ TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
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rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
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rt2x00_desc_write(txd, 5, word);
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@@ -1882,7 +1881,7 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
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/*
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* Write the TX descriptor for the beacon.
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*/
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- rt61pci_write_tx_desc(rt2x00dev, entry->skb, txdesc);
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+ rt61pci_write_tx_desc(entry, txdesc);
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/*
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* Dump beacon to userspace through debugfs.
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@@ -1918,34 +1917,34 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
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entry->skb = NULL;
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}
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-static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
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- const enum data_queue_qid queue)
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+static void rt61pci_kick_tx_queue(struct data_queue *queue)
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{
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+ struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
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u32 reg;
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rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
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- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
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- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
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- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
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- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
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+ rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, (queue->qid == QID_AC_BE));
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+ rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, (queue->qid == QID_AC_BK));
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+ rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, (queue->qid == QID_AC_VI));
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+ rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, (queue->qid == QID_AC_VO));
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rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
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}
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-static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
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- const enum data_queue_qid qid)
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+static void rt61pci_kill_tx_queue(struct data_queue *queue)
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{
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+ struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
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u32 reg;
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- if (qid == QID_BEACON) {
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+ if (queue->qid == QID_BEACON) {
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rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
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return;
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}
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rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
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- rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE));
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- rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK));
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- rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI));
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- rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO));
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+ rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, (queue->qid == QID_AC_BE));
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+ rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, (queue->qid == QID_AC_BK));
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+ rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, (queue->qid == QID_AC_VI));
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+ rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, (queue->qid == QID_AC_VO));
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rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
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}
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