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@@ -59,6 +59,14 @@
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#define PPC_INST_NAP 0x4c000364
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#define PPC_INST_SLEEP 0x4c0003a4
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+/* A2 specific instructions */
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+#define PPC_INST_ERATWE 0x7c0001a6
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+#define PPC_INST_ERATRE 0x7c000166
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+#define PPC_INST_ERATILX 0x7c000066
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+#define PPC_INST_ERATIVAX 0x7c000666
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+#define PPC_INST_ERATSX 0x7c000126
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+#define PPC_INST_ERATSX_DOT 0x7c000127
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+
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/* macros to insert fields into opcodes */
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#define __PPC_RA(a) (((a) & 0x1f) << 16)
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#define __PPC_RB(b) (((b) & 0x1f) << 11)
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@@ -70,6 +78,8 @@
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#define __PPC_XT(s) __PPC_XS(s)
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#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
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#define __PPC_WC(w) (((w) & 0x3) << 21)
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+#define __PPC_WS(w) (((w) & 0x1f) << 11)
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+
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/*
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* Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
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* larx with EH set as an illegal instruction.
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@@ -116,6 +126,21 @@
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#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
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__PPC_RA(a) | __PPC_RB(b))
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+#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
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+ __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
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+#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
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+ __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
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+#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
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+ __PPC_T_TLB(t) | __PPC_RA(a) | \
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+ __PPC_RB(b))
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+#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
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+ __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
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+#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
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+ __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
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+#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
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+ __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
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+
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+
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/*
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* Define what the VSX XX1 form instructions will look like, then add
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* the 128 bit load store instructions based on that.
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