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@@ -191,12 +191,9 @@ static void iwl_pcie_txq_stuck_timer(unsigned long data)
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}
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for (i = q->read_ptr; i != q->write_ptr;
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- i = iwl_queue_inc_wrap(i, q->n_bd)) {
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- struct iwl_tx_cmd *tx_cmd =
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- (struct iwl_tx_cmd *)txq->entries[i].cmd->payload;
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+ i = iwl_queue_inc_wrap(i, q->n_bd))
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IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
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- get_unaligned_le32(&tx_cmd->scratch));
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- }
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+ le32_to_cpu(txq->scratchbufs[i].scratch));
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iwl_op_mode_nic_error(trans->op_mode);
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}
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@@ -367,8 +364,8 @@ static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
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}
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static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
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- struct iwl_cmd_meta *meta, struct iwl_tfd *tfd,
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- enum dma_data_direction dma_dir)
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+ struct iwl_cmd_meta *meta,
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+ struct iwl_tfd *tfd)
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{
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int i;
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int num_tbs;
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@@ -382,17 +379,12 @@ static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
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return;
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}
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- /* Unmap tx_cmd */
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- if (num_tbs)
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- dma_unmap_single(trans->dev,
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- dma_unmap_addr(meta, mapping),
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- dma_unmap_len(meta, len),
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- DMA_BIDIRECTIONAL);
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+ /* first TB is never freed - it's the scratchbuf data */
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- /* Unmap chunks, if any. */
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for (i = 1; i < num_tbs; i++)
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dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
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- iwl_pcie_tfd_tb_get_len(tfd, i), dma_dir);
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+ iwl_pcie_tfd_tb_get_len(tfd, i),
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+ DMA_TO_DEVICE);
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tfd->num_tbs = 0;
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}
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@@ -406,8 +398,7 @@ static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
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* Does NOT advance any TFD circular buffer read/write indexes
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* Does NOT free the TFD itself (which is within circular buffer)
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*/
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-static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
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- enum dma_data_direction dma_dir)
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+static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
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{
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struct iwl_tfd *tfd_tmp = txq->tfds;
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@@ -418,8 +409,7 @@ static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
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lockdep_assert_held(&txq->lock);
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/* We have only q->n_window txq->entries, but we use q->n_bd tfds */
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- iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr],
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- dma_dir);
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+ iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
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/* free SKB */
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if (txq->entries) {
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@@ -479,6 +469,7 @@ static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
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+ size_t scratchbuf_sz;
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int i;
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if (WARN_ON(txq->entries || txq->tfds))
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@@ -514,9 +505,25 @@ static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
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IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
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goto error;
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}
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+
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+ BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
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+ BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
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+ sizeof(struct iwl_cmd_header) +
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+ offsetof(struct iwl_tx_cmd, scratch));
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+
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+ scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
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+
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+ txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
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+ &txq->scratchbufs_dma,
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+ GFP_KERNEL);
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+ if (!txq->scratchbufs)
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+ goto err_free_tfds;
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+
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txq->q.id = txq_id;
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return 0;
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+err_free_tfds:
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+ dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
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error:
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if (txq->entries && txq_id == trans_pcie->cmd_queue)
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for (i = 0; i < slots_num; i++)
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@@ -565,22 +572,13 @@ static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_txq *txq = &trans_pcie->txq[txq_id];
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struct iwl_queue *q = &txq->q;
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- enum dma_data_direction dma_dir;
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if (!q->n_bd)
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return;
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- /* In the command queue, all the TBs are mapped as BIDI
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- * so unmap them as such.
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- */
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- if (txq_id == trans_pcie->cmd_queue)
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- dma_dir = DMA_BIDIRECTIONAL;
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- else
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- dma_dir = DMA_TO_DEVICE;
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-
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spin_lock_bh(&txq->lock);
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while (q->write_ptr != q->read_ptr) {
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- iwl_pcie_txq_free_tfd(trans, txq, dma_dir);
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+ iwl_pcie_txq_free_tfd(trans, txq);
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
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}
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spin_unlock_bh(&txq->lock);
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@@ -610,7 +608,6 @@ static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
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if (txq_id == trans_pcie->cmd_queue)
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for (i = 0; i < txq->q.n_window; i++) {
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kfree(txq->entries[i].cmd);
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- kfree(txq->entries[i].copy_cmd);
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kfree(txq->entries[i].free_buf);
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}
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@@ -619,6 +616,10 @@ static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
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dma_free_coherent(dev, sizeof(struct iwl_tfd) *
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txq->q.n_bd, txq->tfds, txq->q.dma_addr);
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txq->q.dma_addr = 0;
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+
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+ dma_free_coherent(dev,
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+ sizeof(*txq->scratchbufs) * txq->q.n_window,
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+ txq->scratchbufs, txq->scratchbufs_dma);
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}
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kfree(txq->entries);
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@@ -962,7 +963,7 @@ void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
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iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
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- iwl_pcie_txq_free_tfd(trans, txq, DMA_TO_DEVICE);
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+ iwl_pcie_txq_free_tfd(trans, txq);
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}
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iwl_pcie_txq_progress(trans_pcie, txq);
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@@ -1152,29 +1153,29 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
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void *dup_buf = NULL;
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dma_addr_t phys_addr;
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int idx;
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- u16 copy_size, cmd_size, dma_size;
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+ u16 copy_size, cmd_size, scratch_size;
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bool had_nocopy = false;
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int i;
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u32 cmd_pos;
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- const u8 *cmddata[IWL_MAX_CMD_TFDS];
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- u16 cmdlen[IWL_MAX_CMD_TFDS];
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+ const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
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+ u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
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copy_size = sizeof(out_cmd->hdr);
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cmd_size = sizeof(out_cmd->hdr);
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/* need one for the header if the first is NOCOPY */
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- BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
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+ BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
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- for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
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+ for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
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cmddata[i] = cmd->data[i];
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cmdlen[i] = cmd->len[i];
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if (!cmd->len[i])
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continue;
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- /* need at least IWL_HCMD_MIN_COPY_SIZE copied */
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- if (copy_size < IWL_HCMD_MIN_COPY_SIZE) {
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- int copy = IWL_HCMD_MIN_COPY_SIZE - copy_size;
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+ /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
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+ if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
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+ int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
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if (copy > cmdlen[i])
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copy = cmdlen[i];
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@@ -1260,15 +1261,15 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
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/* and copy the data that needs to be copied */
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cmd_pos = offsetof(struct iwl_device_cmd, payload);
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copy_size = sizeof(out_cmd->hdr);
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- for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
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+ for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
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int copy = 0;
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if (!cmd->len)
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continue;
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- /* need at least IWL_HCMD_MIN_COPY_SIZE copied */
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- if (copy_size < IWL_HCMD_MIN_COPY_SIZE) {
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- copy = IWL_HCMD_MIN_COPY_SIZE - copy_size;
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+ /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
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+ if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
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+ copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
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if (copy > cmd->len[i])
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copy = cmd->len[i];
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@@ -1286,50 +1287,38 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
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}
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}
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- WARN_ON_ONCE(txq->entries[idx].copy_cmd);
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-
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- /*
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- * since out_cmd will be the source address of the FH, it will write
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- * the retry count there. So when the user needs to receivce the HCMD
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- * that corresponds to the response in the response handler, it needs
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- * to set CMD_WANT_HCMD.
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- */
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- if (cmd->flags & CMD_WANT_HCMD) {
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- txq->entries[idx].copy_cmd =
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- kmemdup(out_cmd, cmd_pos, GFP_ATOMIC);
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- if (unlikely(!txq->entries[idx].copy_cmd)) {
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- idx = -ENOMEM;
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- goto out;
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- }
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- }
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-
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IWL_DEBUG_HC(trans,
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"Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
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get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
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out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
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cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
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|
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|
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- /*
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- * If the entire command is smaller than IWL_HCMD_MIN_COPY_SIZE, we must
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- * still map at least that many bytes for the hardware to write back to.
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- * We have enough space, so that's not a problem.
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- */
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- dma_size = max_t(u16, copy_size, IWL_HCMD_MIN_COPY_SIZE);
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+ /* start the TFD with the scratchbuf */
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+ scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
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+ memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
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+ iwl_pcie_txq_build_tfd(trans, txq,
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+ iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
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+ scratch_size, 1);
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+
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+ /* map first command fragment, if any remains */
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+ if (copy_size > scratch_size) {
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+ phys_addr = dma_map_single(trans->dev,
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+ ((u8 *)&out_cmd->hdr) + scratch_size,
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+ copy_size - scratch_size,
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+ DMA_TO_DEVICE);
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+ if (dma_mapping_error(trans->dev, phys_addr)) {
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+ iwl_pcie_tfd_unmap(trans, out_meta,
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+ &txq->tfds[q->write_ptr]);
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+ idx = -ENOMEM;
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+ goto out;
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+ }
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|
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|
|
- phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, dma_size,
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- DMA_BIDIRECTIONAL);
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- if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
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- idx = -ENOMEM;
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- goto out;
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+ iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
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+ copy_size - scratch_size, 0);
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}
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|
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- dma_unmap_addr_set(out_meta, mapping, phys_addr);
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- dma_unmap_len_set(out_meta, len, dma_size);
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-
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- iwl_pcie_txq_build_tfd(trans, txq, phys_addr, copy_size, 1);
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-
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/* map the remaining (adjusted) nocopy/dup fragments */
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- for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
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+ for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
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const void *data = cmddata[i];
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|
|
|
|
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if (!cmdlen[i])
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|
@@ -1340,11 +1329,10 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
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|
|
if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
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|
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data = dup_buf;
|
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phys_addr = dma_map_single(trans->dev, (void *)data,
|
|
|
- cmdlen[i], DMA_BIDIRECTIONAL);
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+ cmdlen[i], DMA_TO_DEVICE);
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|
if (dma_mapping_error(trans->dev, phys_addr)) {
|
|
|
iwl_pcie_tfd_unmap(trans, out_meta,
|
|
|
- &txq->tfds[q->write_ptr],
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- DMA_BIDIRECTIONAL);
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|
|
+ &txq->tfds[q->write_ptr]);
|
|
|
idx = -ENOMEM;
|
|
|
goto out;
|
|
|
}
|
|
|
@@ -1418,7 +1406,7 @@ void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
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|
|
cmd = txq->entries[cmd_index].cmd;
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|
meta = &txq->entries[cmd_index].meta;
|
|
|
|
|
|
- iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index], DMA_BIDIRECTIONAL);
|
|
|
+ iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
|
|
|
|
|
|
/* Input error checking is done when commands are added to queue. */
|
|
|
if (meta->flags & CMD_WANT_SKB) {
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|
|
@@ -1597,10 +1585,9 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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|
|
struct iwl_cmd_meta *out_meta;
|
|
|
struct iwl_txq *txq;
|
|
|
struct iwl_queue *q;
|
|
|
- dma_addr_t phys_addr = 0;
|
|
|
- dma_addr_t txcmd_phys;
|
|
|
- dma_addr_t scratch_phys;
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|
|
- u16 len, firstlen, secondlen;
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|
|
+ dma_addr_t tb0_phys, tb1_phys, scratch_phys;
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|
+ void *tb1_addr;
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|
|
+ u16 len, tb1_len, tb2_len;
|
|
|
u8 wait_write_ptr = 0;
|
|
|
__le16 fc = hdr->frame_control;
|
|
|
u8 hdr_len = ieee80211_hdrlen(fc);
|
|
|
@@ -1638,85 +1625,80 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
|
|
|
cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
|
|
|
INDEX_TO_SEQ(q->write_ptr)));
|
|
|
|
|
|
+ tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
|
|
|
+ scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
|
|
|
+ offsetof(struct iwl_tx_cmd, scratch);
|
|
|
+
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|
|
+ tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
|
|
|
+ tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
|
|
|
+
|
|
|
/* Set up first empty entry in queue's array of Tx/cmd buffers */
|
|
|
out_meta = &txq->entries[q->write_ptr].meta;
|
|
|
|
|
|
/*
|
|
|
- * Use the first empty entry in this queue's command buffer array
|
|
|
- * to contain the Tx command and MAC header concatenated together
|
|
|
- * (payload data will be in another buffer).
|
|
|
- * Size of this varies, due to varying MAC header length.
|
|
|
- * If end is not dword aligned, we'll have 2 extra bytes at the end
|
|
|
- * of the MAC header (device reads on dword boundaries).
|
|
|
- * We'll tell device about this padding later.
|
|
|
+ * The second TB (tb1) points to the remainder of the TX command
|
|
|
+ * and the 802.11 header - dword aligned size
|
|
|
+ * (This calculation modifies the TX command, so do it before the
|
|
|
+ * setup of the first TB)
|
|
|
*/
|
|
|
- len = sizeof(struct iwl_tx_cmd) +
|
|
|
- sizeof(struct iwl_cmd_header) + hdr_len;
|
|
|
- firstlen = (len + 3) & ~3;
|
|
|
+ len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
|
|
|
+ hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
|
|
|
+ tb1_len = (len + 3) & ~3;
|
|
|
|
|
|
/* Tell NIC about any 2-byte padding after MAC header */
|
|
|
- if (firstlen != len)
|
|
|
+ if (tb1_len != len)
|
|
|
tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
|
|
|
|
|
|
- /* Physical address of this Tx command's header (not MAC header!),
|
|
|
- * within command buffer array. */
|
|
|
- txcmd_phys = dma_map_single(trans->dev,
|
|
|
- &dev_cmd->hdr, firstlen,
|
|
|
- DMA_BIDIRECTIONAL);
|
|
|
- if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
|
|
|
- goto out_err;
|
|
|
- dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
|
|
|
- dma_unmap_len_set(out_meta, len, firstlen);
|
|
|
+ /* The first TB points to the scratchbuf data - min_copy bytes */
|
|
|
+ memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
|
|
|
+ IWL_HCMD_SCRATCHBUF_SIZE);
|
|
|
+ iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
|
|
|
+ IWL_HCMD_SCRATCHBUF_SIZE, 1);
|
|
|
|
|
|
- if (!ieee80211_has_morefrags(fc)) {
|
|
|
- txq->need_update = 1;
|
|
|
- } else {
|
|
|
- wait_write_ptr = 1;
|
|
|
- txq->need_update = 0;
|
|
|
- }
|
|
|
+ /* there must be data left over for TB1 or this code must be changed */
|
|
|
+ BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
|
|
|
|
|
|
- /* Set up TFD's 2nd entry to point directly to remainder of skb,
|
|
|
- * if any (802.11 null frames have no payload). */
|
|
|
- secondlen = skb->len - hdr_len;
|
|
|
- if (secondlen > 0) {
|
|
|
- phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
|
|
|
- secondlen, DMA_TO_DEVICE);
|
|
|
- if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
|
|
|
- dma_unmap_single(trans->dev,
|
|
|
- dma_unmap_addr(out_meta, mapping),
|
|
|
- dma_unmap_len(out_meta, len),
|
|
|
- DMA_BIDIRECTIONAL);
|
|
|
+ /* map the data for TB1 */
|
|
|
+ tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
|
|
|
+ tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
|
|
|
+ if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
|
|
|
+ goto out_err;
|
|
|
+ iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, 0);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Set up TFD's third entry to point directly to remainder
|
|
|
+ * of skb, if any (802.11 null frames have no payload).
|
|
|
+ */
|
|
|
+ tb2_len = skb->len - hdr_len;
|
|
|
+ if (tb2_len > 0) {
|
|
|
+ dma_addr_t tb2_phys = dma_map_single(trans->dev,
|
|
|
+ skb->data + hdr_len,
|
|
|
+ tb2_len, DMA_TO_DEVICE);
|
|
|
+ if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
|
|
|
+ iwl_pcie_tfd_unmap(trans, out_meta,
|
|
|
+ &txq->tfds[q->write_ptr]);
|
|
|
goto out_err;
|
|
|
}
|
|
|
+ iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, 0);
|
|
|
}
|
|
|
|
|
|
- /* Attach buffers to TFD */
|
|
|
- iwl_pcie_txq_build_tfd(trans, txq, txcmd_phys, firstlen, 1);
|
|
|
- if (secondlen > 0)
|
|
|
- iwl_pcie_txq_build_tfd(trans, txq, phys_addr, secondlen, 0);
|
|
|
-
|
|
|
- scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
|
|
|
- offsetof(struct iwl_tx_cmd, scratch);
|
|
|
-
|
|
|
- /* take back ownership of DMA buffer to enable update */
|
|
|
- dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
|
|
|
- DMA_BIDIRECTIONAL);
|
|
|
- tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
|
|
|
- tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
|
|
|
-
|
|
|
/* Set up entry for this TFD in Tx byte-count array */
|
|
|
iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
|
|
|
|
|
|
- dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
|
|
|
- DMA_BIDIRECTIONAL);
|
|
|
-
|
|
|
trace_iwlwifi_dev_tx(trans->dev, skb,
|
|
|
&txq->tfds[txq->q.write_ptr],
|
|
|
sizeof(struct iwl_tfd),
|
|
|
- &dev_cmd->hdr, firstlen,
|
|
|
- skb->data + hdr_len, secondlen);
|
|
|
+ &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
|
|
|
+ skb->data + hdr_len, tb2_len);
|
|
|
trace_iwlwifi_dev_tx_data(trans->dev, skb,
|
|
|
- skb->data + hdr_len, secondlen);
|
|
|
+ skb->data + hdr_len, tb2_len);
|
|
|
+
|
|
|
+ if (!ieee80211_has_morefrags(fc)) {
|
|
|
+ txq->need_update = 1;
|
|
|
+ } else {
|
|
|
+ wait_write_ptr = 1;
|
|
|
+ txq->need_update = 0;
|
|
|
+ }
|
|
|
|
|
|
/* start timer if queue currently empty */
|
|
|
if (txq->need_update && q->read_ptr == q->write_ptr &&
|
David S. Miller