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@@ -1310,10 +1310,6 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
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if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
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oem_reg |= HV_OEM_BITS_LPLU;
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-
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- /* Set Restart auto-neg to activate the bits */
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- if (!hw->phy.ops.check_reset_block(hw))
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- oem_reg |= HV_OEM_BITS_RESTART_AN;
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} else {
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if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
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E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
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@@ -1324,6 +1320,11 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
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oem_reg |= HV_OEM_BITS_LPLU;
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}
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+ /* Set Restart auto-neg to activate the bits */
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+ if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
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+ !hw->phy.ops.check_reset_block(hw))
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+ oem_reg |= HV_OEM_BITS_RESTART_AN;
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+
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ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
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release:
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@@ -3682,7 +3683,11 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
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if (hw->mac.type >= e1000_pchlan) {
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e1000_oem_bits_config_ich8lan(hw, false);
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- e1000_phy_hw_reset_ich8lan(hw);
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+
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+ /* Reset PHY to activate OEM bits on 82577/8 */
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+ if (hw->mac.type == e1000_pchlan)
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+ e1000e_phy_hw_reset_generic(hw);
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+
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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return;
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