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@@ -1675,6 +1675,17 @@ int r100_gpu_reset(struct radeon_device *rdev)
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return 0;
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}
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+void r100_set_common_regs(struct radeon_device *rdev)
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+{
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+ /* set these so they don't interfere with anything */
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+ WREG32(RADEON_OV0_SCALE_CNTL, 0);
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+ WREG32(RADEON_SUBPIC_CNTL, 0);
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+ WREG32(RADEON_VIPH_CONTROL, 0);
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+ WREG32(RADEON_I2C_CNTL_1, 0);
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+ WREG32(RADEON_DVI_I2C_CNTL_1, 0);
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+ WREG32(RADEON_CAP0_TRIG_CNTL, 0);
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+ WREG32(RADEON_CAP1_TRIG_CNTL, 0);
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+}
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/*
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* VRAM info
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@@ -3129,6 +3140,9 @@ static int r100_startup(struct radeon_device *rdev)
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{
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int r;
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+ /* set common regs */
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+ r100_set_common_regs(rdev);
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+ /* program mc */
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r100_mc_program(rdev);
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/* Resume clock */
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r100_clock_startup(rdev);
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