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@@ -0,0 +1,556 @@
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+/*
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+ * SS4200-E Hardware API
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+ * Copyright (c) 2009, Intel Corporation.
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+ * Copyright IBM Corporation, 2009
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ * You should have received a copy of the GNU General Public License along with
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+ * this program; if not, write to the Free Software Foundation, Inc.,
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+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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+ *
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+ * Author: Dave Hansen <dave@sr71.net>
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+ */
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+
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+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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+
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+#include <linux/dmi.h>
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+#include <linux/init.h>
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+#include <linux/ioport.h>
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+#include <linux/kernel.h>
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+#include <linux/leds.h>
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+#include <linux/module.h>
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+#include <linux/pci.h>
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+#include <linux/types.h>
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+#include <linux/uaccess.h>
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+
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+MODULE_AUTHOR("Rodney Girod <rgirod@confocus.com>, Dave Hansen <dave@sr71.net>");
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+MODULE_DESCRIPTION("Intel NAS/Home Server ICH7 GPIO Driver");
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+MODULE_LICENSE("GPL");
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+
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+/*
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+ * ICH7 LPC/GPIO PCI Config register offsets
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+ */
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+#define PMBASE 0x040
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+#define GPIO_BASE 0x048
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+#define GPIO_CTRL 0x04c
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+#define GPIO_EN 0x010
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+
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+/*
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+ * The ICH7 GPIO register block is 64 bytes in size.
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+ */
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+#define ICH7_GPIO_SIZE 64
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+
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+/*
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+ * Define register offsets within the ICH7 register block.
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+ */
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+#define GPIO_USE_SEL 0x000
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+#define GP_IO_SEL 0x004
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+#define GP_LVL 0x00c
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+#define GPO_BLINK 0x018
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+#define GPI_INV 0x030
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+#define GPIO_USE_SEL2 0x034
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+#define GP_IO_SEL2 0x038
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+#define GP_LVL2 0x03c
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+
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+/*
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+ * PCI ID of the Intel ICH7 LPC Device within which the GPIO block lives.
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+ */
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+static struct pci_device_id ich7_lpc_pci_id[] =
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+{
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+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0) },
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+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1) },
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+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_30) },
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+ { } /* NULL entry */
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+};
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+
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+MODULE_DEVICE_TABLE(pci, ich7_lpc_pci_id);
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+
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+static int __init ss4200_led_dmi_callback(const struct dmi_system_id *id)
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+{
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+ pr_info("detected '%s'\n", id->ident);
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+ return 1;
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+}
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+
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+static unsigned int __initdata nodetect;
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+module_param_named(nodetect, nodetect, bool, 0);
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+MODULE_PARM_DESC(nodetect, "Skip DMI-based hardware detection");
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+
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+/*
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+ * struct nas_led_whitelist - List of known good models
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+ *
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+ * Contains the known good models this driver is compatible with.
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+ * When adding a new model try to be as strict as possible. This
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+ * makes it possible to keep the false positives (the model is
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+ * detected as working, but in reality it is not) as low as
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+ * possible.
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+ */
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+static struct dmi_system_id __initdata nas_led_whitelist[] = {
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+ {
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+ .callback = ss4200_led_dmi_callback,
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+ .ident = "Intel SS4200-E",
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+ .matches = {
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+ DMI_MATCH(DMI_SYS_VENDOR, "Intel"),
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+ DMI_MATCH(DMI_PRODUCT_NAME, "SS4200-E"),
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+ DMI_MATCH(DMI_PRODUCT_VERSION, "1.00.00")
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+ }
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+ },
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+};
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+
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+/*
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+ * Base I/O address assigned to the Power Management register block
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+ */
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+static u32 g_pm_io_base;
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+
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+/*
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+ * Base I/O address assigned to the ICH7 GPIO register block
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+ */
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+static u32 nas_gpio_io_base;
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+
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+/*
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+ * When we successfully register a region, we are returned a resource.
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+ * We use these to identify which regions we need to release on our way
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+ * back out.
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+ */
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+static struct resource *gp_gpio_resource;
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+
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+struct nasgpio_led {
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+ char *name;
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+ u32 gpio_bit;
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+ struct led_classdev led_cdev;
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+};
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+
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+/*
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+ * gpio_bit(s) are the ICH7 GPIO bit assignments
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+ */
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+static struct nasgpio_led nasgpio_leds[] = {
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+ { .name = "hdd1:blue:sata", .gpio_bit = 0 },
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+ { .name = "hdd1:amber:sata", .gpio_bit = 1 },
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+ { .name = "hdd2:blue:sata", .gpio_bit = 2 },
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+ { .name = "hdd2:amber:sata", .gpio_bit = 3 },
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+ { .name = "hdd3:blue:sata", .gpio_bit = 4 },
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+ { .name = "hdd3:amber:sata", .gpio_bit = 5 },
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+ { .name = "hdd4:blue:sata", .gpio_bit = 6 },
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+ { .name = "hdd4:amber:sata", .gpio_bit = 7 },
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+ { .name = "power:blue:power", .gpio_bit = 27},
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+ { .name = "power:amber:power", .gpio_bit = 28},
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+};
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+
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+#define NAS_RECOVERY 0x00000400 /* GPIO10 */
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+
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+static struct nasgpio_led *
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+led_classdev_to_nasgpio_led(struct led_classdev *led_cdev)
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+{
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+ return container_of(led_cdev, struct nasgpio_led, led_cdev);
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+}
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+
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+static struct nasgpio_led *get_led_named(char *name)
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+{
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+ int i;
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+ for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++) {
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+ if (strcmp(nasgpio_leds[i].name, name))
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+ continue;
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+ return &nasgpio_leds[i];
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+ }
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+ return NULL;
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+}
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+
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+/*
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+ * This protects access to the gpio ports.
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+ */
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+static DEFINE_SPINLOCK(nasgpio_gpio_lock);
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+
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+/*
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+ * There are two gpio ports, one for blinking and the other
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+ * for power. @port tells us if we're doing blinking or
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+ * power control.
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+ *
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+ * Caller must hold nasgpio_gpio_lock
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+ */
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+static void __nasgpio_led_set_attr(struct led_classdev *led_cdev,
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+ u32 port, u32 value)
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+{
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+ struct nasgpio_led *led = led_classdev_to_nasgpio_led(led_cdev);
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+ u32 gpio_out;
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+
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+ gpio_out = inl(nas_gpio_io_base + port);
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+ if (value)
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+ gpio_out |= (1<<led->gpio_bit);
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+ else
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+ gpio_out &= ~(1<<led->gpio_bit);
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+
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+ outl(gpio_out, nas_gpio_io_base + port);
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+}
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+
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+static void nasgpio_led_set_attr(struct led_classdev *led_cdev,
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+ u32 port, u32 value)
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+{
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+ spin_lock(&nasgpio_gpio_lock);
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+ __nasgpio_led_set_attr(led_cdev, port, value);
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+ spin_unlock(&nasgpio_gpio_lock);
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+}
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+
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+u32 nasgpio_led_get_attr(struct led_classdev *led_cdev, u32 port)
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+{
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+ struct nasgpio_led *led = led_classdev_to_nasgpio_led(led_cdev);
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+ u32 gpio_in;
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+
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+ spin_lock(&nasgpio_gpio_lock);
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+ gpio_in = inl(nas_gpio_io_base + port);
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+ spin_unlock(&nasgpio_gpio_lock);
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+ if (gpio_in & (1<<led->gpio_bit))
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+ return 1;
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+ return 0;
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+}
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+
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+/*
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+ * There is actual brightness control in the hardware,
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+ * but it is via smbus commands and not implemented
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+ * in this driver.
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+ */
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+static void nasgpio_led_set_brightness(struct led_classdev *led_cdev,
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+ enum led_brightness brightness)
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+{
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+ u32 setting = 0;
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+ if (brightness >= LED_HALF)
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+ setting = 1;
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+ /*
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+ * Hold the lock across both operations. This ensures
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+ * consistency so that both the "turn off blinking"
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+ * and "turn light off" operations complete as a set.
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+ */
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+ spin_lock(&nasgpio_gpio_lock);
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+ /*
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+ * LED class documentation asks that past blink state
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+ * be disabled when brightness is turned to zero.
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+ */
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+ if (brightness == 0)
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+ __nasgpio_led_set_attr(led_cdev, GPO_BLINK, 0);
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+ __nasgpio_led_set_attr(led_cdev, GP_LVL, setting);
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+ spin_unlock(&nasgpio_gpio_lock);
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+}
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+
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+static int nasgpio_led_set_blink(struct led_classdev *led_cdev,
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+ unsigned long *delay_on,
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+ unsigned long *delay_off)
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+{
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+ u32 setting = 1;
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+ if (!(*delay_on == 0 && *delay_off == 0) &&
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+ !(*delay_on == 500 && *delay_off == 500))
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+ return -EINVAL;
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+ /*
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+ * These are very approximate.
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+ */
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+ *delay_on = 500;
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+ *delay_off = 500;
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+
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+ nasgpio_led_set_attr(led_cdev, GPO_BLINK, setting);
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+
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+ return 0;
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+}
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+
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+
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+/*
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+ * Initialize the ICH7 GPIO registers for NAS usage. The BIOS should have
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+ * already taken care of this, but we will do so in a non destructive manner
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+ * so that we have what we need whether the BIOS did it or not.
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+ */
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+static int __devinit ich7_gpio_init(struct device *dev)
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+{
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+ int i;
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+ u32 config_data = 0;
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+ u32 all_nas_led = 0;
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+
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+ for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++)
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+ all_nas_led |= (1<<nasgpio_leds[i].gpio_bit);
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+
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+ spin_lock(&nasgpio_gpio_lock);
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+ /*
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+ * We need to enable all of the GPIO lines used by the NAS box,
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+ * so we will read the current Use Selection and add our usage
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+ * to it. This should be benign with regard to the original
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+ * BIOS configuration.
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+ */
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+ config_data = inl(nas_gpio_io_base + GPIO_USE_SEL);
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+ dev_dbg(dev, ": Data read from GPIO_USE_SEL = 0x%08x\n", config_data);
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+ config_data |= all_nas_led + NAS_RECOVERY;
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+ outl(config_data, nas_gpio_io_base + GPIO_USE_SEL);
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+ config_data = inl(nas_gpio_io_base + GPIO_USE_SEL);
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+ dev_dbg(dev, ": GPIO_USE_SEL = 0x%08x\n\n", config_data);
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+
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+ /*
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+ * The LED GPIO outputs need to be configured for output, so we
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+ * will ensure that all LED lines are cleared for output and the
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+ * RECOVERY line ready for input. This too should be benign with
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+ * regard to BIOS configuration.
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+ */
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+ config_data = inl(nas_gpio_io_base + GP_IO_SEL);
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+ dev_dbg(dev, ": Data read from GP_IO_SEL = 0x%08x\n",
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+ config_data);
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+ config_data &= ~all_nas_led;
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+ config_data |= NAS_RECOVERY;
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+ outl(config_data, nas_gpio_io_base + GP_IO_SEL);
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+ config_data = inl(nas_gpio_io_base + GP_IO_SEL);
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+ dev_dbg(dev, ": GP_IO_SEL = 0x%08x\n", config_data);
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+
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+ /*
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+ * In our final system, the BIOS will initialize the state of all
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+ * of the LEDs. For now, we turn them all off (or Low).
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+ */
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+ config_data = inl(nas_gpio_io_base + GP_LVL);
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+ dev_dbg(dev, ": Data read from GP_LVL = 0x%08x\n", config_data);
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+ /*
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+ * In our final system, the BIOS will initialize the blink state of all
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+ * of the LEDs. For now, we turn blink off for all of them.
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+ */
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+ config_data = inl(nas_gpio_io_base + GPO_BLINK);
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+ dev_dbg(dev, ": Data read from GPO_BLINK = 0x%08x\n", config_data);
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+
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+ /*
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+ * At this moment, I am unsure if anything needs to happen with GPI_INV
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+ */
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+ config_data = inl(nas_gpio_io_base + GPI_INV);
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+ dev_dbg(dev, ": Data read from GPI_INV = 0x%08x\n", config_data);
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+
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+ spin_unlock(&nasgpio_gpio_lock);
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+ return 0;
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+}
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+
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+static void ich7_lpc_cleanup(struct device *dev)
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+{
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+ /*
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+ * If we were given exclusive use of the GPIO
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+ * I/O Address range, we must return it.
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+ */
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+ if (gp_gpio_resource) {
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+ dev_dbg(dev, ": Releasing GPIO I/O addresses\n");
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+ release_region(nas_gpio_io_base, ICH7_GPIO_SIZE);
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+ gp_gpio_resource = NULL;
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+ }
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+}
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+
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+/*
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+ * The OS has determined that the LPC of the Intel ICH7 Southbridge is present
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+ * so we can retrive the required operational information and prepare the GPIO.
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+ */
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+static struct pci_dev *nas_gpio_pci_dev;
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+static int __devinit ich7_lpc_probe(struct pci_dev *dev,
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+ const struct pci_device_id *id)
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+{
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+ int status;
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+ u32 gc = 0;
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+
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+ status = pci_enable_device(dev);
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+ if (status) {
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+ dev_err(&dev->dev, "pci_enable_device failed\n");
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+ return -EIO;
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+ }
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+
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+ nas_gpio_pci_dev = dev;
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+ status = pci_read_config_dword(dev, PMBASE, &g_pm_io_base);
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+ if (status)
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+ goto out;
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+ g_pm_io_base &= 0x00000ff80;
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+
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+ status = pci_read_config_dword(dev, GPIO_CTRL, &gc);
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+ if (!(GPIO_EN & gc)) {
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+ status = -EEXIST;
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+ dev_info(&dev->dev,
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+ "ERROR: The LPC GPIO Block has not been enabled.\n");
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+ goto out;
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+ }
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+
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+ status = pci_read_config_dword(dev, GPIO_BASE, &nas_gpio_io_base);
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+ if (0 > status) {
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+ dev_info(&dev->dev, "Unable to read GPIOBASE.\n");
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+ goto out;
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+ }
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+ dev_dbg(&dev->dev, ": GPIOBASE = 0x%08x\n", nas_gpio_io_base);
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+ nas_gpio_io_base &= 0x00000ffc0;
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+
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+ /*
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+ * Insure that we have exclusive access to the GPIO I/O address range.
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+ */
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+ gp_gpio_resource = request_region(nas_gpio_io_base, ICH7_GPIO_SIZE,
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+ KBUILD_MODNAME);
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+ if (NULL == gp_gpio_resource) {
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+ dev_info(&dev->dev,
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+ "ERROR Unable to register GPIO I/O addresses.\n");
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+ status = -1;
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+ goto out;
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+ }
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+
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+ /*
|
|
|
+ * Initialize the GPIO for NAS/Home Server Use
|
|
|
+ */
|
|
|
+ ich7_gpio_init(&dev->dev);
|
|
|
+
|
|
|
+out:
|
|
|
+ if (status) {
|
|
|
+ ich7_lpc_cleanup(&dev->dev);
|
|
|
+ pci_disable_device(dev);
|
|
|
+ }
|
|
|
+ return status;
|
|
|
+}
|
|
|
+
|
|
|
+static void ich7_lpc_remove(struct pci_dev *dev)
|
|
|
+{
|
|
|
+ ich7_lpc_cleanup(&dev->dev);
|
|
|
+ pci_disable_device(dev);
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * pci_driver structure passed to the PCI modules
|
|
|
+ */
|
|
|
+static struct pci_driver nas_gpio_pci_driver = {
|
|
|
+ .name = KBUILD_MODNAME,
|
|
|
+ .id_table = ich7_lpc_pci_id,
|
|
|
+ .probe = ich7_lpc_probe,
|
|
|
+ .remove = ich7_lpc_remove,
|
|
|
+};
|
|
|
+
|
|
|
+static struct led_classdev *get_classdev_for_led_nr(int nr)
|
|
|
+{
|
|
|
+ struct nasgpio_led *nas_led = &nasgpio_leds[nr];
|
|
|
+ struct led_classdev *led = &nas_led->led_cdev;
|
|
|
+ return led;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+static void set_power_light_amber_noblink(void)
|
|
|
+{
|
|
|
+ struct nasgpio_led *amber = get_led_named("power:amber:power");
|
|
|
+ struct nasgpio_led *blue = get_led_named("power:blue:power");
|
|
|
+
|
|
|
+ if (!amber || !blue)
|
|
|
+ return;
|
|
|
+ /*
|
|
|
+ * LED_OFF implies disabling future blinking
|
|
|
+ */
|
|
|
+ pr_debug("setting blue off and amber on\n");
|
|
|
+
|
|
|
+ nasgpio_led_set_brightness(&blue->led_cdev, LED_OFF);
|
|
|
+ nasgpio_led_set_brightness(&amber->led_cdev, LED_FULL);
|
|
|
+}
|
|
|
+
|
|
|
+static ssize_t nas_led_blink_show(struct device *dev,
|
|
|
+ struct device_attribute *attr, char *buf)
|
|
|
+{
|
|
|
+ struct led_classdev *led = dev_get_drvdata(dev);
|
|
|
+ int blinking = 0;
|
|
|
+ if (nasgpio_led_get_attr(led, GPO_BLINK))
|
|
|
+ blinking = 1;
|
|
|
+ return sprintf(buf, "%u\n", blinking);
|
|
|
+}
|
|
|
+
|
|
|
+static ssize_t nas_led_blink_store(struct device *dev,
|
|
|
+ struct device_attribute *attr,
|
|
|
+ const char *buf, size_t size)
|
|
|
+{
|
|
|
+ int ret;
|
|
|
+ struct led_classdev *led = dev_get_drvdata(dev);
|
|
|
+ unsigned long blink_state;
|
|
|
+
|
|
|
+ ret = strict_strtoul(buf, 10, &blink_state);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ nasgpio_led_set_attr(led, GPO_BLINK, blink_state);
|
|
|
+
|
|
|
+ return size;
|
|
|
+}
|
|
|
+
|
|
|
+static DEVICE_ATTR(blink, 0644, nas_led_blink_show, nas_led_blink_store);
|
|
|
+
|
|
|
+static int register_nasgpio_led(int led_nr)
|
|
|
+{
|
|
|
+ int ret;
|
|
|
+ struct nasgpio_led *nas_led = &nasgpio_leds[led_nr];
|
|
|
+ struct led_classdev *led = get_classdev_for_led_nr(led_nr);
|
|
|
+
|
|
|
+ led->name = nas_led->name;
|
|
|
+ led->brightness = LED_OFF;
|
|
|
+ if (nasgpio_led_get_attr(led, GP_LVL))
|
|
|
+ led->brightness = LED_FULL;
|
|
|
+ led->brightness_set = nasgpio_led_set_brightness;
|
|
|
+ led->blink_set = nasgpio_led_set_blink;
|
|
|
+ ret = led_classdev_register(&nas_gpio_pci_dev->dev, led);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ ret = device_create_file(led->dev, &dev_attr_blink);
|
|
|
+ if (ret)
|
|
|
+ led_classdev_unregister(led);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static void unregister_nasgpio_led(int led_nr)
|
|
|
+{
|
|
|
+ struct led_classdev *led = get_classdev_for_led_nr(led_nr);
|
|
|
+ led_classdev_unregister(led);
|
|
|
+ device_remove_file(led->dev, &dev_attr_blink);
|
|
|
+}
|
|
|
+/*
|
|
|
+ * module load/initialization
|
|
|
+ */
|
|
|
+static int __init nas_gpio_init(void)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+ int ret = 0;
|
|
|
+ int nr_devices = 0;
|
|
|
+
|
|
|
+ nr_devices = dmi_check_system(nas_led_whitelist);
|
|
|
+ if (nodetect) {
|
|
|
+ pr_info("skipping hardware autodetection\n");
|
|
|
+ pr_info("Please send 'dmidecode' output to dave@sr71.net\n");
|
|
|
+ nr_devices++;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (nr_devices <= 0) {
|
|
|
+ pr_info("no LED devices found\n");
|
|
|
+ return -ENODEV;
|
|
|
+ }
|
|
|
+
|
|
|
+ pr_info("registering PCI driver\n");
|
|
|
+ ret = pci_register_driver(&nas_gpio_pci_driver);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++) {
|
|
|
+ ret = register_nasgpio_led(i);
|
|
|
+ if (ret)
|
|
|
+ goto out_err;
|
|
|
+ }
|
|
|
+ /*
|
|
|
+ * When the system powers on, the BIOS leaves the power
|
|
|
+ * light blue and blinking. This will turn it solid
|
|
|
+ * amber once the driver is loaded.
|
|
|
+ */
|
|
|
+ set_power_light_amber_noblink();
|
|
|
+ return 0;
|
|
|
+out_err:
|
|
|
+ for (; i >= 0; i--)
|
|
|
+ unregister_nasgpio_led(i);
|
|
|
+ pci_unregister_driver(&nas_gpio_pci_driver);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * module unload
|
|
|
+ */
|
|
|
+static void __exit nas_gpio_exit(void)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+ pr_info("Unregistering driver\n");
|
|
|
+ for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++)
|
|
|
+ unregister_nasgpio_led(i);
|
|
|
+ pci_unregister_driver(&nas_gpio_pci_driver);
|
|
|
+}
|
|
|
+
|
|
|
+module_init(nas_gpio_init);
|
|
|
+module_exit(nas_gpio_exit);
|
Linus Torvalds