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@@ -3,7 +3,7 @@ Tegra SOC USB PHY
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The device node for Tegra SOC USB PHY:
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Required properties :
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- - compatible : Should be "nvidia,tegra20-usb-phy".
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+ - compatible : Should be "nvidia,tegra<chip>-usb-phy".
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- reg : Defines the following set of registers, in the order listed:
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- The PHY's own register set.
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Always present.
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@@ -24,17 +24,26 @@ Required properties :
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Required properties for phy_type == ulpi:
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- nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
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-Required PHY timing params for utmi phy:
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+Required PHY timing params for utmi phy, for all chips:
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- nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
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start of sync launches RxActive
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- nvidia,elastic-limit : Variable FIFO Depth of elastic input store
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- nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
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before declare IDLE.
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- nvidia,term-range-adj : Range adjusment on terminations
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- - nvidia,xcvr-setup : HS driver output control
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+ - Either one of the following for HS driver output control:
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+ - nvidia,xcvr-setup : integer, uses the provided value.
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+ - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read
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+ from the on-chip fuses
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+ If both are provided, nvidia,xcvr-setup-use-fuses takes precedence.
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- nvidia,xcvr-lsfslew : LS falling slew rate control.
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- nvidia,xcvr-lsrslew : LS rising slew rate control.
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+Required PHY timing params for utmi phy, only on Tegra30 and above:
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+ - nvidia,xcvr-hsslew : HS slew rate control.
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+ - nvidia,hssquelch-level : HS squelch detector level.
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+ - nvidia,hsdiscon-level : HS disconnect detector level.
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+
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Optional properties:
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- nvidia,has-legacy-mode : boolean indicates whether this controller can
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operate in legacy mode (as APX 2500 / 2600). In legacy mode some
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