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@@ -170,8 +170,8 @@ not_angel:
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.text
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adr r0, LC0
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- ARM( ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp} )
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- THUMB( ldmia r0, {r1, r2, r3, r4, r5, r6, ip} )
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+ ARM( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
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+ THUMB( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip} )
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THUMB( ldr sp, [r0, #28] )
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subs r0, r0, r1 @ calculate the delta offset
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@@ -182,12 +182,13 @@ not_angel:
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/*
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* We're running at a different address. We need to fix
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* up various pointers:
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- * r5 - zImage base address
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- * r6 - GOT start
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+ * r5 - zImage base address (_start)
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+ * r6 - size of decompressed image
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+ * r11 - GOT start
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* ip - GOT end
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*/
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add r5, r5, r0
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- add r6, r6, r0
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+ add r11, r11, r0
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add ip, ip, r0
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#ifndef CONFIG_ZBOOT_ROM
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@@ -205,10 +206,10 @@ not_angel:
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/*
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* Relocate all entries in the GOT table.
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*/
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-1: ldr r1, [r6, #0] @ relocate entries in the GOT
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+1: ldr r1, [r11, #0] @ relocate entries in the GOT
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add r1, r1, r0 @ table. This fixes up the
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- str r1, [r6], #4 @ C references.
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- cmp r6, ip
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+ str r1, [r11], #4 @ C references.
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+ cmp r11, ip
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blo 1b
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#else
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@@ -216,12 +217,12 @@ not_angel:
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* Relocate entries in the GOT table. We only relocate
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* the entries that are outside the (relocated) BSS region.
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*/
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-1: ldr r1, [r6, #0] @ relocate entries in the GOT
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+1: ldr r1, [r11, #0] @ relocate entries in the GOT
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cmp r1, r2 @ entry < bss_start ||
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cmphs r3, r1 @ _end < entry
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addlo r1, r1, r0 @ table. This fixes up the
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- str r1, [r6], #4 @ C references.
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- cmp r6, ip
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+ str r1, [r11], #4 @ C references.
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+ cmp r11, ip
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blo 1b
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#endif
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@@ -247,6 +248,7 @@ not_relocated: mov r0, #0
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* Check to see if we will overwrite ourselves.
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* r4 = final kernel address
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* r5 = start of this image
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+ * r6 = size of decompressed image
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* r2 = end of malloc space (and therefore this image)
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* We basically want:
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* r4 >= r2 -> OK
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@@ -254,8 +256,7 @@ not_relocated: mov r0, #0
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*/
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cmp r4, r2
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bhs wont_overwrite
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- sub r3, sp, r5 @ > compressed kernel size
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- add r0, r4, r3, lsl #2 @ allow for 4x expansion
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+ add r0, r4, r6
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cmp r0, r5
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bls wont_overwrite
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@@ -271,7 +272,6 @@ not_relocated: mov r0, #0
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* r1-r3 = unused
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* r4 = kernel execution address
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* r5 = decompressed kernel start
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- * r6 = processor ID
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* r7 = architecture ID
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* r8 = atags pointer
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* r9-r12,r14 = corrupted
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@@ -312,7 +312,8 @@ LC0: .word LC0 @ r1
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.word _end @ r3
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.word zreladdr @ r4
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.word _start @ r5
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- .word _got_start @ r6
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+ .word _image_size @ r6
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+ .word _got_start @ r11
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.word _got_end @ ip
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.word user_stack+4096 @ sp
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LC1: .word reloc_end - reloc_start
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@@ -336,7 +337,6 @@ params: ldr r0, =params_phys
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*
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* On entry,
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* r4 = kernel execution address
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- * r6 = processor ID
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* r7 = architecture number
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* r8 = atags pointer
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* r9 = run-time address of "start" (???)
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@@ -542,7 +542,6 @@ __common_mmu_cache_on:
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* r1-r3 = unused
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* r4 = kernel execution address
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* r5 = decompressed kernel start
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- * r6 = processor ID
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* r7 = architecture ID
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* r8 = atags pointer
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* r9-r12,r14 = corrupted
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@@ -581,19 +580,19 @@ call_kernel: bl cache_clean_flush
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* r1 = corrupted
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* r2 = corrupted
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* r3 = block offset
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- * r6 = corrupted
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+ * r9 = corrupted
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* r12 = corrupted
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*/
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call_cache_fn: adr r12, proc_types
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#ifdef CONFIG_CPU_CP15
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- mrc p15, 0, r6, c0, c0 @ get processor ID
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+ mrc p15, 0, r9, c0, c0 @ get processor ID
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#else
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- ldr r6, =CONFIG_PROCESSOR_ID
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+ ldr r9, =CONFIG_PROCESSOR_ID
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#endif
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1: ldr r1, [r12, #0] @ get value
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ldr r2, [r12, #4] @ get mask
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- eor r1, r1, r6 @ (real ^ match)
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+ eor r1, r1, r9 @ (real ^ match)
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tst r1, r2 @ & mask
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ARM( addeq pc, r12, r3 ) @ call cache function
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THUMB( addeq r12, r3 )
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@@ -778,8 +777,7 @@ proc_types:
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* Turn off the Cache and MMU. ARMv3 does not support
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* reading the control register, but ARMv4 does.
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*
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- * On entry, r6 = processor ID
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- * On exit, r0, r1, r2, r3, r12 corrupted
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+ * On exit, r0, r1, r2, r3, r9, r12 corrupted
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* This routine must preserve: r4, r6, r7
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*/
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.align 5
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@@ -852,10 +850,8 @@ __armv3_mmu_cache_off:
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/*
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* Clean and flush the cache to maintain consistency.
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*
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- * On entry,
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- * r6 = processor ID
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* On exit,
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- * r1, r2, r3, r11, r12 corrupted
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+ * r1, r2, r3, r9, r11, r12 corrupted
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* This routine must preserve:
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* r0, r4, r5, r6, r7
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*/
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@@ -967,7 +963,7 @@ __armv4_mmu_cache_flush:
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mov r2, #64*1024 @ default: 32K dcache size (*2)
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mov r11, #32 @ default: 32 byte line size
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mrc p15, 0, r3, c0, c0, 1 @ read cache type
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- teq r3, r6 @ cache ID register present?
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+ teq r3, r9 @ cache ID register present?
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beq no_cache_id
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mov r1, r3, lsr #18
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and r1, r1, #7
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Russell King