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@@ -542,6 +542,40 @@ static void rs780_enable_voltage_scaling(struct radeon_device *rdev,
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WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
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}
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+static void rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
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+ struct radeon_ps *new_ps,
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+ struct radeon_ps *old_ps)
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+{
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+ struct igp_ps *new_state = rs780_get_ps(new_ps);
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+ struct igp_ps *current_state = rs780_get_ps(old_ps);
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+
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+ if ((new_ps->vclk == old_ps->vclk) &&
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+ (new_ps->dclk == old_ps->dclk))
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+ return;
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+
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+ if (new_state->sclk_high >= current_state->sclk_high)
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+ return;
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+
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+ radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
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+}
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+
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+static void rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
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+ struct radeon_ps *new_ps,
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+ struct radeon_ps *old_ps)
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+{
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+ struct igp_ps *new_state = rs780_get_ps(new_ps);
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+ struct igp_ps *current_state = rs780_get_ps(old_ps);
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+
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+ if ((new_ps->vclk == old_ps->vclk) &&
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+ (new_ps->dclk == old_ps->dclk))
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+ return;
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+
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+ if (new_state->sclk_high < current_state->sclk_high)
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+ return;
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+
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+ radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
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+}
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+
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int rs780_dpm_enable(struct radeon_device *rdev)
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{
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struct igp_power_info *pi = rs780_get_pi(rdev);
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@@ -611,6 +645,8 @@ int rs780_dpm_set_power_state(struct radeon_device *rdev)
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rs780_get_pm_mode_parameters(rdev);
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+ rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
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+
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if (pi->voltage_control) {
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rs780_force_voltage_to_high(rdev);
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mdelay(5);
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@@ -626,6 +662,8 @@ int rs780_dpm_set_power_state(struct radeon_device *rdev)
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if (pi->voltage_control)
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rs780_enable_voltage_scaling(rdev, new_ps);
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+ rs780_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
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+
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return 0;
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}
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