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@@ -3562,9 +3562,9 @@ static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,
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static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
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{
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+ struct ath9k_hw_capabilities *pCap = &ah->caps;
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int chain;
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u32 regval;
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- u32 ant_div_ctl1;
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static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
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AR_PHY_SWITCH_CHAIN_0,
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AR_PHY_SWITCH_CHAIN_1,
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@@ -3636,9 +3636,8 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
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regval &= (~AR_FAST_DIV_ENABLE);
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regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
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REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
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- ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
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- /* check whether antenna diversity is enabled */
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- if ((ant_div_ctl1 >> 0x6) == 0x3) {
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+
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+ if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
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regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
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/*
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* clear bits 25-30 main_lnaconf, alt_lnaconf,
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@@ -3655,10 +3654,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
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AR_PHY_ANT_DIV_ALT_LNACONF_S);
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REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
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}
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-
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-
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}
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-
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}
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static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
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