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@@ -770,12 +770,13 @@ set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
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/*
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* Calculate MDMA timings for all cells
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*/
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-static int
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+static void
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set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
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- u8 speed, int drive_cycle_time)
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+ u8 speed)
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{
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int cycleTime, accessTime = 0, recTime = 0;
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unsigned accessTicks, recTicks;
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+ struct hd_driveid *id = drive->id;
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struct mdma_timings_t* tm = NULL;
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int i;
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@@ -785,11 +786,14 @@ set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
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case 1: cycleTime = 150; break;
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case 2: cycleTime = 120; break;
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default:
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- return 1;
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+ BUG();
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+ break;
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}
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- /* Adjust for drive */
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- if (drive_cycle_time && drive_cycle_time > cycleTime)
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- cycleTime = drive_cycle_time;
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+
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+ /* Check if drive provides explicit DMA cycle time */
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+ if ((id->field_valid & 2) && id->eide_dma_time)
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+ cycleTime = max_t(int, id->eide_dma_time, cycleTime);
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+
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/* OHare limits according to some old Apple sources */
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if ((intf_type == controller_ohare) && (cycleTime < 150))
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cycleTime = 150;
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@@ -817,8 +821,6 @@ set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
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break;
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i++;
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}
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- if (i < 0)
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- return 1;
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cycleTime = tm[i].cycleTime;
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accessTime = tm[i].accessTime;
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recTime = tm[i].recoveryTime;
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@@ -900,16 +902,12 @@ set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
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printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
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drive->name, speed & 0xf, *timings);
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#endif
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- return 0;
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}
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#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
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/*
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* Speedproc. This function is called by the core to set any of the standard
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* DMA timing (MDMA or UDMA) to both the drive and the controller.
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- * You may notice we don't use this function on normal "dma check" operation,
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- * our dedicated function is more precise as it uses the drive provided
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- * cycle time value. We should probably fix this one to deal with that too...
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*/
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static int pmac_ide_tune_chipset(ide_drive_t *drive, const u8 speed)
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{
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@@ -947,7 +945,7 @@ static int pmac_ide_tune_chipset(ide_drive_t *drive, const u8 speed)
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case XFER_MW_DMA_2:
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case XFER_MW_DMA_1:
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case XFER_MW_DMA_0:
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- ret = set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed, 0);
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+ set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
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break;
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case XFER_SW_DMA_2:
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case XFER_SW_DMA_1:
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@@ -1680,8 +1678,6 @@ pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
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{
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ide_hwif_t *hwif = HWIF(drive);
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pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
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- int drive_cycle_time;
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- struct hd_driveid *id = drive->id;
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u32 *timings, *timings2;
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u32 timing_local[2];
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int ret;
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@@ -1690,24 +1686,12 @@ pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
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timings = &pmif->timings[drive->select.b.unit & 0x01];
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timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
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- /* Check if drive provide explicit cycle time */
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- if ((id->field_valid & 2) && (id->eide_dma_time))
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- drive_cycle_time = id->eide_dma_time;
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- else
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- drive_cycle_time = 0;
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-
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/* Copy timings to local image */
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timing_local[0] = *timings;
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timing_local[1] = *timings2;
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/* Calculate controller timings */
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- ret = set_timings_mdma( drive, pmif->kind,
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- &timing_local[0],
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- &timing_local[1],
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- mode,
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- drive_cycle_time);
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- if (ret)
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- return 0;
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+ set_timings_mdma(drive, pmif->kind, &timing_local[0], &timing_local[1], mode);
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/* Set feature on drive */
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printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf);
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