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@@ -216,6 +216,28 @@ static __init void nmi_cpu_busy(void *data)
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}
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#endif
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+static unsigned int adjust_for_32bit_ctr(unsigned int hz)
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+{
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+ u64 counter_val;
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+ unsigned int retval = hz;
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+
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+ /*
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+ * On Intel CPUs with P6/ARCH_PERFMON only 32 bits in the counter
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+ * are writable, with higher bits sign extending from bit 31.
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+ * So, we can only program the counter with 31 bit values and
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+ * 32nd bit should be 1, for 33.. to be 1.
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+ * Find the appropriate nmi_hz
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+ */
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+ counter_val = (u64)cpu_khz * 1000;
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+ do_div(counter_val, retval);
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+ if (counter_val > 0x7fffffffULL) {
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+ u64 count = (u64)cpu_khz * 1000;
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+ do_div(count, 0x7fffffffUL);
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+ retval = count + 1;
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+ }
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+ return retval;
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+}
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+
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static int __init check_nmi_watchdog(void)
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{
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unsigned int *prev_nmi_count;
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@@ -281,18 +303,10 @@ static int __init check_nmi_watchdog(void)
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struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
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nmi_hz = 1;
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- /*
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- * On Intel CPUs with ARCH_PERFMON only 32 bits in the counter
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- * are writable, with higher bits sign extending from bit 31.
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- * So, we can only program the counter with 31 bit values and
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- * 32nd bit should be 1, for 33.. to be 1.
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- * Find the appropriate nmi_hz
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- */
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- if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0 &&
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- ((u64)cpu_khz * 1000) > 0x7fffffffULL) {
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- u64 count = (u64)cpu_khz * 1000;
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- do_div(count, 0x7fffffffUL);
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- nmi_hz = count + 1;
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+
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+ if (wd->perfctr_msr == MSR_P6_PERFCTR0 ||
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+ wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
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+ nmi_hz = adjust_for_32bit_ctr(nmi_hz);
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}
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}
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@@ -442,6 +456,17 @@ static void write_watchdog_counter(unsigned int perfctr_msr, const char *descr)
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wrmsrl(perfctr_msr, 0 - count);
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}
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+static void write_watchdog_counter32(unsigned int perfctr_msr,
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+ const char *descr)
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+{
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+ u64 count = (u64)cpu_khz * 1000;
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+
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+ do_div(count, nmi_hz);
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+ if(descr)
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+ Dprintk("setting %s to -0x%08Lx\n", descr, count);
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+ wrmsr(perfctr_msr, (u32)(-count), 0);
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+}
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+
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/* Note that these events don't tick when the CPU idles. This means
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the frequency varies with CPU load. */
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@@ -531,7 +556,8 @@ static int setup_p6_watchdog(void)
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/* setup the timer */
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wrmsr(evntsel_msr, evntsel, 0);
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- write_watchdog_counter(perfctr_msr, "P6_PERFCTR0");
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+ nmi_hz = adjust_for_32bit_ctr(nmi_hz);
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+ write_watchdog_counter32(perfctr_msr, "P6_PERFCTR0");
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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evntsel |= P6_EVNTSEL0_ENABLE;
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wrmsr(evntsel_msr, evntsel, 0);
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@@ -704,7 +730,8 @@ static int setup_intel_arch_watchdog(void)
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/* setup the timer */
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wrmsr(evntsel_msr, evntsel, 0);
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- write_watchdog_counter(perfctr_msr, "INTEL_ARCH_PERFCTR0");
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+ nmi_hz = adjust_for_32bit_ctr(nmi_hz);
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+ write_watchdog_counter32(perfctr_msr, "INTEL_ARCH_PERFCTR0");
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsr(evntsel_msr, evntsel, 0);
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@@ -956,6 +983,8 @@ __kprobes int nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
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dummy &= ~P4_CCCR_OVF;
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wrmsrl(wd->cccr_msr, dummy);
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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+ /* start the cycle over again */
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+ write_watchdog_counter(wd->perfctr_msr, NULL);
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}
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else if (wd->perfctr_msr == MSR_P6_PERFCTR0 ||
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wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
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@@ -964,9 +993,12 @@ __kprobes int nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
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* other P6 variant.
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* ArchPerfom/Core Duo also needs this */
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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+ /* P6/ARCH_PERFMON has 32 bit counter write */
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+ write_watchdog_counter32(wd->perfctr_msr, NULL);
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+ } else {
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+ /* start the cycle over again */
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+ write_watchdog_counter(wd->perfctr_msr, NULL);
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}
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- /* start the cycle over again */
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- write_watchdog_counter(wd->perfctr_msr, NULL);
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rc = 1;
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} else if (nmi_watchdog == NMI_IO_APIC) {
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/* don't know how to accurately check for this.
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