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@@ -0,0 +1,408 @@
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+/*
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+ * linux/arch/arm/mach-omap2/mmc-twl4030.c
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+ *
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+ * Copyright (C) 2007-2008 Texas Instruments
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+ * Copyright (C) 2008 Nokia Corporation
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+ * Author: Texas Instruments
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/interrupt.h>
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+#include <linux/delay.h>
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+#include <linux/gpio.h>
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+#include <linux/i2c/twl4030.h>
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+
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+#include <mach/hardware.h>
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+#include <mach/control.h>
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+#include <mach/mmc.h>
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+#include <mach/board.h>
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+
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+#include "mmc-twl4030.h"
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+
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+#if defined(CONFIG_TWL4030_CORE) && \
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+ (defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE))
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+
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+#define LDO_CLR 0x00
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+#define VSEL_S2_CLR 0x40
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+
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+#define VMMC1_DEV_GRP 0x27
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+#define VMMC1_CLR 0x00
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+#define VMMC1_315V 0x03
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+#define VMMC1_300V 0x02
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+#define VMMC1_285V 0x01
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+#define VMMC1_185V 0x00
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+#define VMMC1_DEDICATED 0x2A
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+
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+#define VMMC2_DEV_GRP 0x2B
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+#define VMMC2_CLR 0x40
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+#define VMMC2_315V 0x0c
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+#define VMMC2_300V 0x0b
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+#define VMMC2_285V 0x0a
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+#define VMMC2_260V 0x08
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+#define VMMC2_185V 0x06
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+#define VMMC2_DEDICATED 0x2E
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+
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+#define VMMC_DEV_GRP_P1 0x20
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+
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+static u16 control_pbias_offset;
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+static u16 control_devconf1_offset;
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+
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+#define HSMMC_NAME_LEN 9
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+
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+static struct twl_mmc_controller {
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+ struct omap_mmc_platform_data *mmc;
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+ u8 twl_vmmc_dev_grp;
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+ u8 twl_mmc_dedicated;
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+ char name[HSMMC_NAME_LEN];
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+} hsmmc[] = {
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+ {
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+ .twl_vmmc_dev_grp = VMMC1_DEV_GRP,
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+ .twl_mmc_dedicated = VMMC1_DEDICATED,
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+ },
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+ {
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+ .twl_vmmc_dev_grp = VMMC2_DEV_GRP,
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+ .twl_mmc_dedicated = VMMC2_DEDICATED,
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+ },
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+};
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+
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+static int twl_mmc_card_detect(int irq)
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+{
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+ unsigned i;
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+
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+ for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
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+ struct omap_mmc_platform_data *mmc;
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+
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+ mmc = hsmmc[i].mmc;
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+ if (!mmc)
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+ continue;
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+ if (irq != mmc->slots[0].card_detect_irq)
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+ continue;
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+
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+ /* NOTE: assumes card detect signal is active-low */
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+ return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
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+ }
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+ return -ENOSYS;
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+}
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+
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+static int twl_mmc_get_ro(struct device *dev, int slot)
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+{
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+ struct omap_mmc_platform_data *mmc = dev->platform_data;
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+
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+ /* NOTE: assumes write protect signal is active-high */
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+ return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
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+}
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+
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+/*
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+ * MMC Slot Initialization.
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+ */
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+static int twl_mmc_late_init(struct device *dev)
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+{
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+ struct omap_mmc_platform_data *mmc = dev->platform_data;
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+ int ret = 0;
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+ int i;
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+
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+ ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd");
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+ if (ret)
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+ goto done;
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+ ret = gpio_direction_input(mmc->slots[0].switch_pin);
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+ if (ret)
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+ goto err;
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+
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+ for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
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+ if (hsmmc[i].name == mmc->slots[0].name) {
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+ hsmmc[i].mmc = mmc;
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+ break;
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+ }
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+ }
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+
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+ return 0;
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+
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+err:
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+ gpio_free(mmc->slots[0].switch_pin);
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+done:
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+ mmc->slots[0].card_detect_irq = 0;
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+ mmc->slots[0].card_detect = NULL;
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+
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+ dev_err(dev, "err %d configuring card detect\n", ret);
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+ return ret;
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+}
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+
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+static void twl_mmc_cleanup(struct device *dev)
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+{
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+ struct omap_mmc_platform_data *mmc = dev->platform_data;
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+
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+ gpio_free(mmc->slots[0].switch_pin);
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+}
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+
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+#ifdef CONFIG_PM
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+
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+static int twl_mmc_suspend(struct device *dev, int slot)
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+{
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+ struct omap_mmc_platform_data *mmc = dev->platform_data;
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+
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+ disable_irq(mmc->slots[0].card_detect_irq);
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+ return 0;
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+}
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+
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+static int twl_mmc_resume(struct device *dev, int slot)
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+{
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+ struct omap_mmc_platform_data *mmc = dev->platform_data;
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+
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+ enable_irq(mmc->slots[0].card_detect_irq);
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+ return 0;
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+}
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+
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+#else
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+#define twl_mmc_suspend NULL
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+#define twl_mmc_resume NULL
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+#endif
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+
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+/*
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+ * Sets the MMC voltage in twl4030
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+ */
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+static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd)
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+{
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+ int ret;
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+ u8 vmmc, dev_grp_val;
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+
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+ switch (1 << vdd) {
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+ case MMC_VDD_35_36:
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+ case MMC_VDD_34_35:
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+ case MMC_VDD_33_34:
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+ case MMC_VDD_32_33:
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+ case MMC_VDD_31_32:
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+ case MMC_VDD_30_31:
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+ if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
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+ vmmc = VMMC1_315V;
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+ else
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+ vmmc = VMMC2_315V;
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+ break;
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+ case MMC_VDD_29_30:
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+ if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
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+ vmmc = VMMC1_315V;
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+ else
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+ vmmc = VMMC2_300V;
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+ break;
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+ case MMC_VDD_27_28:
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+ case MMC_VDD_26_27:
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+ if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
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+ vmmc = VMMC1_285V;
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+ else
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+ vmmc = VMMC2_285V;
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+ break;
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+ case MMC_VDD_25_26:
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+ case MMC_VDD_24_25:
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+ case MMC_VDD_23_24:
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+ case MMC_VDD_22_23:
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+ case MMC_VDD_21_22:
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+ case MMC_VDD_20_21:
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+ if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
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+ vmmc = VMMC1_285V;
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+ else
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+ vmmc = VMMC2_260V;
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+ break;
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+ case MMC_VDD_165_195:
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+ if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
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+ vmmc = VMMC1_185V;
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+ else
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+ vmmc = VMMC2_185V;
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+ break;
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+ default:
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+ vmmc = 0;
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+ break;
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+ }
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+
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+ if (vmmc)
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+ dev_grp_val = VMMC_DEV_GRP_P1; /* Power up */
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+ else
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+ dev_grp_val = LDO_CLR; /* Power down */
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+
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+ ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
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+ dev_grp_val, c->twl_vmmc_dev_grp);
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+ if (ret)
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+ return ret;
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+
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+ ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
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+ vmmc, c->twl_mmc_dedicated);
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+
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+ return ret;
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+}
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+
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+static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
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+ int vdd)
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+{
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+ u32 reg;
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+ int ret = 0;
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+ struct twl_mmc_controller *c = &hsmmc[0];
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+ struct omap_mmc_platform_data *mmc = dev->platform_data;
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+
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+ if (power_on) {
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+ if (cpu_is_omap2430()) {
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+ reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
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+ if ((1 << vdd) >= MMC_VDD_30_31)
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+ reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
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+ else
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+ reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
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+ omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
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+ }
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+
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+ if (mmc->slots[0].internal_clock) {
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+ reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
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+ reg |= OMAP2_MMCSDIO1ADPCLKISEL;
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+ omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
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+ }
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+
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+ reg = omap_ctrl_readl(control_pbias_offset);
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+ reg |= OMAP2_PBIASSPEEDCTRL0;
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+ reg &= ~OMAP2_PBIASLITEPWRDNZ0;
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+ omap_ctrl_writel(reg, control_pbias_offset);
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+
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+ ret = twl_mmc_set_voltage(c, vdd);
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+
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+ /* 100ms delay required for PBIAS configuration */
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+ msleep(100);
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+ reg = omap_ctrl_readl(control_pbias_offset);
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+ reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
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+ if ((1 << vdd) <= MMC_VDD_165_195)
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+ reg &= ~OMAP2_PBIASLITEVMODE0;
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+ else
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+ reg |= OMAP2_PBIASLITEVMODE0;
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+ omap_ctrl_writel(reg, control_pbias_offset);
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+ } else {
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+ reg = omap_ctrl_readl(control_pbias_offset);
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+ reg &= ~OMAP2_PBIASLITEPWRDNZ0;
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+ omap_ctrl_writel(reg, control_pbias_offset);
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+
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+ ret = twl_mmc_set_voltage(c, 0);
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+
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+ /* 100ms delay required for PBIAS configuration */
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+ msleep(100);
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+ reg = omap_ctrl_readl(control_pbias_offset);
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+ reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
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+ OMAP2_PBIASLITEVMODE0);
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+ omap_ctrl_writel(reg, control_pbias_offset);
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+ }
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+
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+ return ret;
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+}
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+
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+static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vdd)
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+{
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+ int ret;
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+ struct twl_mmc_controller *c = &hsmmc[1];
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+ struct omap_mmc_platform_data *mmc = dev->platform_data;
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+
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+ if (power_on) {
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+ if (mmc->slots[0].internal_clock) {
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+ u32 reg;
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+
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+ reg = omap_ctrl_readl(control_devconf1_offset);
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+ reg |= OMAP2_MMCSDIO2ADPCLKISEL;
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+ omap_ctrl_writel(reg, control_devconf1_offset);
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+ }
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+ ret = twl_mmc_set_voltage(c, vdd);
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+ } else {
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+ ret = twl_mmc_set_voltage(c, 0);
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+ }
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+
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+ return ret;
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+}
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+
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+static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
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+
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+void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
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+{
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+ struct twl4030_hsmmc_info *c;
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+ int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
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+
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+ if (cpu_is_omap2430()) {
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+ control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
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+ control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
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+ nr_hsmmc = 2;
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+ } else {
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+ control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
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+ control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
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+ }
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+
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+ for (c = controllers; c->mmc; c++) {
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+ struct twl_mmc_controller *twl = hsmmc + c->mmc - 1;
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+ struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
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+
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+ if (!c->mmc || c->mmc > nr_hsmmc) {
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+ pr_debug("MMC%d: no such controller\n", c->mmc);
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+ continue;
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+ }
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+ if (mmc) {
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+ pr_debug("MMC%d: already configured\n", c->mmc);
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+ continue;
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+ }
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+
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+ mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
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+ if (!mmc) {
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+ pr_err("Cannot allocate memory for mmc device!\n");
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+ return;
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+ }
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+
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+ sprintf(twl->name, "mmc%islot%i", c->mmc, 1);
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+ mmc->slots[0].name = twl->name;
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+ mmc->nr_slots = 1;
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+ mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
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+ MMC_VDD_26_27 | MMC_VDD_27_28 |
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+ MMC_VDD_29_30 |
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+ MMC_VDD_30_31 | MMC_VDD_31_32;
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+ mmc->slots[0].wires = c->wires;
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+ mmc->slots[0].internal_clock = !c->ext_clock;
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+ mmc->dma_mask = 0xffffffff;
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+
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+ /* note: twl4030 card detect GPIOs normally switch VMMCx ... */
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+ if (gpio_is_valid(c->gpio_cd)) {
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+ mmc->init = twl_mmc_late_init;
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+ mmc->cleanup = twl_mmc_cleanup;
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+ mmc->suspend = twl_mmc_suspend;
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+ mmc->resume = twl_mmc_resume;
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+
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+ mmc->slots[0].switch_pin = c->gpio_cd;
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+ mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd);
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+ mmc->slots[0].card_detect = twl_mmc_card_detect;
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+ } else
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+ mmc->slots[0].switch_pin = -EINVAL;
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+
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+ /* write protect normally uses an OMAP gpio */
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+ if (gpio_is_valid(c->gpio_wp)) {
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+ gpio_request(c->gpio_wp, "mmc_wp");
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+ gpio_direction_input(c->gpio_wp);
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+
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+ mmc->slots[0].gpio_wp = c->gpio_wp;
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+ mmc->slots[0].get_ro = twl_mmc_get_ro;
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+ } else
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+ mmc->slots[0].gpio_wp = -EINVAL;
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+
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+ /* NOTE: we assume OMAP's MMC1 and MMC2 use
|
|
|
+ * the TWL4030's VMMC1 and VMMC2, respectively;
|
|
|
+ * and that OMAP's MMC3 isn't used.
|
|
|
+ */
|
|
|
+
|
|
|
+ switch (c->mmc) {
|
|
|
+ case 1:
|
|
|
+ mmc->slots[0].set_power = twl_mmc1_set_power;
|
|
|
+ break;
|
|
|
+ case 2:
|
|
|
+ mmc->slots[0].set_power = twl_mmc2_set_power;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ pr_err("MMC%d configuration not supported!\n", c->mmc);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+ hsmmc_data[c->mmc - 1] = mmc;
|
|
|
+ }
|
|
|
+
|
|
|
+ omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
|
|
|
+}
|
|
|
+
|
|
|
+#endif
|
Tony Lindgren