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@@ -44,462 +44,310 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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ar9462_2p0_baseband_core_txfir_coeff_japan_2484
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if (AR_SREV_9330_11(ah)) {
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/* mac */
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- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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- ar9331_1p1_mac_core,
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- ARRAY_SIZE(ar9331_1p1_mac_core), 2);
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+ ar9331_1p1_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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- ar9331_1p1_mac_postamble,
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- ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
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+ ar9331_1p1_mac_postamble);
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/* bb */
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- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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- ar9331_1p1_baseband_core,
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- ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
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+ ar9331_1p1_baseband_core);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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- ar9331_1p1_baseband_postamble,
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- ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
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+ ar9331_1p1_baseband_postamble);
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/* radio */
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- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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- ar9331_1p1_radio_core,
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- ARRAY_SIZE(ar9331_1p1_radio_core), 2);
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- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
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+ ar9331_1p1_radio_core);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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- ar9331_1p1_soc_preamble,
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- ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
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- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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+ ar9331_1p1_soc_preamble);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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- ar9331_1p1_soc_postamble,
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- ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
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+ ar9331_1p1_soc_postamble);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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- ar9331_common_rx_gain_1p1,
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- ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
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+ ar9331_common_rx_gain_1p1);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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- ar9331_modes_lowest_ob_db_tx_gain_1p1,
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- ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
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- 5);
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+ ar9331_modes_lowest_ob_db_tx_gain_1p1);
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/* additional clock settings */
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if (ah->is_clk_25mhz)
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INIT_INI_ARRAY(&ah->iniAdditional,
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- ar9331_1p1_xtal_25M,
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- ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
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+ ar9331_1p1_xtal_25M);
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else
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INIT_INI_ARRAY(&ah->iniAdditional,
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- ar9331_1p1_xtal_40M,
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- ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
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+ ar9331_1p1_xtal_40M);
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} else if (AR_SREV_9330_12(ah)) {
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/* mac */
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- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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- ar9331_1p2_mac_core,
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- ARRAY_SIZE(ar9331_1p2_mac_core), 2);
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+ ar9331_1p2_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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- ar9331_1p2_mac_postamble,
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- ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
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+ ar9331_1p2_mac_postamble);
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/* bb */
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- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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- ar9331_1p2_baseband_core,
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- ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
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+ ar9331_1p2_baseband_core);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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- ar9331_1p2_baseband_postamble,
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- ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
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+ ar9331_1p2_baseband_postamble);
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/* radio */
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- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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- ar9331_1p2_radio_core,
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- ARRAY_SIZE(ar9331_1p2_radio_core), 2);
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- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
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+ ar9331_1p2_radio_core);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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- ar9331_1p2_soc_preamble,
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- ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
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- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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+ ar9331_1p2_soc_preamble);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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- ar9331_1p2_soc_postamble,
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- ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
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+ ar9331_1p2_soc_postamble);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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- ar9331_common_rx_gain_1p2,
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- ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
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+ ar9331_common_rx_gain_1p2);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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- ar9331_modes_lowest_ob_db_tx_gain_1p2,
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- ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
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- 5);
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+ ar9331_modes_lowest_ob_db_tx_gain_1p2);
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/* additional clock settings */
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if (ah->is_clk_25mhz)
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INIT_INI_ARRAY(&ah->iniAdditional,
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- ar9331_1p2_xtal_25M,
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- ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
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+ ar9331_1p2_xtal_25M);
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else
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INIT_INI_ARRAY(&ah->iniAdditional,
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- ar9331_1p2_xtal_40M,
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- ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
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+ ar9331_1p2_xtal_40M);
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} else if (AR_SREV_9340(ah)) {
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/* mac */
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- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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- ar9340_1p0_mac_core,
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- ARRAY_SIZE(ar9340_1p0_mac_core), 2);
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+ ar9340_1p0_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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- ar9340_1p0_mac_postamble,
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- ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
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+ ar9340_1p0_mac_postamble);
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/* bb */
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- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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- ar9340_1p0_baseband_core,
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- ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
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+ ar9340_1p0_baseband_core);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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- ar9340_1p0_baseband_postamble,
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- ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
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+ ar9340_1p0_baseband_postamble);
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/* radio */
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- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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- ar9340_1p0_radio_core,
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- ARRAY_SIZE(ar9340_1p0_radio_core), 2);
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+ ar9340_1p0_radio_core);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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- ar9340_1p0_radio_postamble,
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- ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
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+ ar9340_1p0_radio_postamble);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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- ar9340_1p0_soc_preamble,
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- ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
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- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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+ ar9340_1p0_soc_preamble);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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- ar9340_1p0_soc_postamble,
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- ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
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+ ar9340_1p0_soc_postamble);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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- ar9340Common_wo_xlna_rx_gain_table_1p0,
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- ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
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- 5);
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+ ar9340Common_wo_xlna_rx_gain_table_1p0);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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- ar9340Modes_high_ob_db_tx_gain_table_1p0,
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- ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
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- 5);
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+ ar9340Modes_high_ob_db_tx_gain_table_1p0);
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INIT_INI_ARRAY(&ah->iniModesFastClock,
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- ar9340Modes_fast_clock_1p0,
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- ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
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- 3);
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+ ar9340Modes_fast_clock_1p0);
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if (!ah->is_clk_25mhz)
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INIT_INI_ARRAY(&ah->iniAdditional,
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- ar9340_1p0_radio_core_40M,
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- ARRAY_SIZE(ar9340_1p0_radio_core_40M),
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- 2);
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+ ar9340_1p0_radio_core_40M);
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} else if (AR_SREV_9485_11(ah)) {
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/* mac */
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- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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- ar9485_1_1_mac_core,
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- ARRAY_SIZE(ar9485_1_1_mac_core), 2);
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+ ar9485_1_1_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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- ar9485_1_1_mac_postamble,
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- ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
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+ ar9485_1_1_mac_postamble);
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/* bb */
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- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
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- ARRAY_SIZE(ar9485_1_1), 2);
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+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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- ar9485_1_1_baseband_core,
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- ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
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+ ar9485_1_1_baseband_core);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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- ar9485_1_1_baseband_postamble,
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- ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
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+ ar9485_1_1_baseband_postamble);
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/* radio */
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- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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- ar9485_1_1_radio_core,
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- ARRAY_SIZE(ar9485_1_1_radio_core), 2);
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+ ar9485_1_1_radio_core);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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- ar9485_1_1_radio_postamble,
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- ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
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+ ar9485_1_1_radio_postamble);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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- ar9485_1_1_soc_preamble,
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- ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
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- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
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+ ar9485_1_1_soc_preamble);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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- ar9485Common_wo_xlna_rx_gain_1_1,
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- ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
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+ ar9485Common_wo_xlna_rx_gain_1_1);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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- ar9485_modes_lowest_ob_db_tx_gain_1_1,
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- ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
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- 5);
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+ ar9485_modes_lowest_ob_db_tx_gain_1_1);
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/* Load PCIE SERDES settings from INI */
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/* Awake Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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- ar9485_1_1_pcie_phy_clkreq_disable_L1,
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- ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
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- 2);
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+ ar9485_1_1_pcie_phy_clkreq_disable_L1);
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/* Sleep Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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- ar9485_1_1_pcie_phy_clkreq_disable_L1,
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- ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
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- 2);
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+ ar9485_1_1_pcie_phy_clkreq_disable_L1);
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} else if (AR_SREV_9462_20(ah)) {
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- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
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- ARRAY_SIZE(ar9462_2p0_mac_core), 2);
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+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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- ar9462_2p0_mac_postamble,
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- ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
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+ ar9462_2p0_mac_postamble);
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- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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- ar9462_2p0_baseband_core,
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- ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
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+ ar9462_2p0_baseband_core);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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- ar9462_2p0_baseband_postamble,
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- ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
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+ ar9462_2p0_baseband_postamble);
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- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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- ar9462_2p0_radio_core,
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- ARRAY_SIZE(ar9462_2p0_radio_core), 2);
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+ ar9462_2p0_radio_core);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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- ar9462_2p0_radio_postamble,
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- ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
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+ ar9462_2p0_radio_postamble);
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INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
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- ar9462_2p0_radio_postamble_sys2ant,
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- ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
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- 5);
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+ ar9462_2p0_radio_postamble_sys2ant);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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- ar9462_2p0_soc_preamble,
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- ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
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- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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+ ar9462_2p0_soc_preamble);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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- ar9462_2p0_soc_postamble,
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- ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
|
|
|
+ ar9462_2p0_soc_postamble);
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9462_common_rx_gain_table_2p0,
|
|
|
- ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
|
|
|
+ ar9462_common_rx_gain_table_2p0);
|
|
|
|
|
|
/* Awake -> Sleep Setting */
|
|
|
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
|
|
- PCIE_PLL_ON_CREQ_DIS_L1_2P0,
|
|
|
- ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
|
|
|
- 2);
|
|
|
+ PCIE_PLL_ON_CREQ_DIS_L1_2P0);
|
|
|
/* Sleep -> Awake Setting */
|
|
|
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
|
|
- PCIE_PLL_ON_CREQ_DIS_L1_2P0,
|
|
|
- ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
|
|
|
- 2);
|
|
|
+ PCIE_PLL_ON_CREQ_DIS_L1_2P0);
|
|
|
|
|
|
/* Fast clock modal settings */
|
|
|
INIT_INI_ARRAY(&ah->iniModesFastClock,
|
|
|
- ar9462_modes_fast_clock_2p0,
|
|
|
- ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
|
|
|
+ ar9462_modes_fast_clock_2p0);
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
|
|
|
- AR9462_BB_CTX_COEFJ(2p0),
|
|
|
- ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
|
|
|
+ AR9462_BB_CTX_COEFJ(2p0));
|
|
|
|
|
|
- INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
|
|
|
- ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
|
|
|
+ INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ);
|
|
|
} else if (AR_SREV_9550(ah)) {
|
|
|
/* mac */
|
|
|
- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
|
|
|
- ar955x_1p0_mac_core,
|
|
|
- ARRAY_SIZE(ar955x_1p0_mac_core), 2);
|
|
|
+ ar955x_1p0_mac_core);
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
|
|
|
- ar955x_1p0_mac_postamble,
|
|
|
- ARRAY_SIZE(ar955x_1p0_mac_postamble), 5);
|
|
|
+ ar955x_1p0_mac_postamble);
|
|
|
|
|
|
/* bb */
|
|
|
- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
|
|
|
- ar955x_1p0_baseband_core,
|
|
|
- ARRAY_SIZE(ar955x_1p0_baseband_core), 2);
|
|
|
+ ar955x_1p0_baseband_core);
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
|
|
|
- ar955x_1p0_baseband_postamble,
|
|
|
- ARRAY_SIZE(ar955x_1p0_baseband_postamble), 5);
|
|
|
+ ar955x_1p0_baseband_postamble);
|
|
|
|
|
|
/* radio */
|
|
|
- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
|
|
|
- ar955x_1p0_radio_core,
|
|
|
- ARRAY_SIZE(ar955x_1p0_radio_core), 2);
|
|
|
+ ar955x_1p0_radio_core);
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
|
|
|
- ar955x_1p0_radio_postamble,
|
|
|
- ARRAY_SIZE(ar955x_1p0_radio_postamble), 5);
|
|
|
+ ar955x_1p0_radio_postamble);
|
|
|
|
|
|
/* soc */
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
|
|
|
- ar955x_1p0_soc_preamble,
|
|
|
- ARRAY_SIZE(ar955x_1p0_soc_preamble), 2);
|
|
|
- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
|
|
|
+ ar955x_1p0_soc_preamble);
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
|
|
|
- ar955x_1p0_soc_postamble,
|
|
|
- ARRAY_SIZE(ar955x_1p0_soc_postamble), 5);
|
|
|
+ ar955x_1p0_soc_postamble);
|
|
|
|
|
|
/* rx/tx gain */
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar955x_1p0_common_wo_xlna_rx_gain_table,
|
|
|
- ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
|
|
|
- 2);
|
|
|
+ ar955x_1p0_common_wo_xlna_rx_gain_table);
|
|
|
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
|
|
|
- ar955x_1p0_common_wo_xlna_rx_gain_bounds,
|
|
|
- ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
|
|
|
- 5);
|
|
|
+ ar955x_1p0_common_wo_xlna_rx_gain_bounds);
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar955x_1p0_modes_xpa_tx_gain_table,
|
|
|
- ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
|
|
|
- 9);
|
|
|
+ ar955x_1p0_modes_xpa_tx_gain_table);
|
|
|
|
|
|
/* Fast clock modal settings */
|
|
|
INIT_INI_ARRAY(&ah->iniModesFastClock,
|
|
|
- ar955x_1p0_modes_fast_clock,
|
|
|
- ARRAY_SIZE(ar955x_1p0_modes_fast_clock), 3);
|
|
|
+ ar955x_1p0_modes_fast_clock);
|
|
|
} else if (AR_SREV_9580(ah)) {
|
|
|
/* mac */
|
|
|
- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
|
|
|
- ar9580_1p0_mac_core,
|
|
|
- ARRAY_SIZE(ar9580_1p0_mac_core), 2);
|
|
|
+ ar9580_1p0_mac_core);
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
|
|
|
- ar9580_1p0_mac_postamble,
|
|
|
- ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
|
|
|
+ ar9580_1p0_mac_postamble);
|
|
|
|
|
|
/* bb */
|
|
|
- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
|
|
|
- ar9580_1p0_baseband_core,
|
|
|
- ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
|
|
|
+ ar9580_1p0_baseband_core);
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
|
|
|
- ar9580_1p0_baseband_postamble,
|
|
|
- ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
|
|
|
+ ar9580_1p0_baseband_postamble);
|
|
|
|
|
|
/* radio */
|
|
|
- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
|
|
|
- ar9580_1p0_radio_core,
|
|
|
- ARRAY_SIZE(ar9580_1p0_radio_core), 2);
|
|
|
+ ar9580_1p0_radio_core);
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
|
|
|
- ar9580_1p0_radio_postamble,
|
|
|
- ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
|
|
|
+ ar9580_1p0_radio_postamble);
|
|
|
|
|
|
/* soc */
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
|
|
|
- ar9580_1p0_soc_preamble,
|
|
|
- ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
|
|
|
- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
|
|
|
+ ar9580_1p0_soc_preamble);
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
|
|
|
- ar9580_1p0_soc_postamble,
|
|
|
- ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
|
|
|
+ ar9580_1p0_soc_postamble);
|
|
|
|
|
|
/* rx/tx gain */
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9580_1p0_rx_gain_table,
|
|
|
- ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
|
|
|
+ ar9580_1p0_rx_gain_table);
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9580_1p0_low_ob_db_tx_gain_table,
|
|
|
- ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
|
|
|
- 5);
|
|
|
+ ar9580_1p0_low_ob_db_tx_gain_table);
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesFastClock,
|
|
|
- ar9580_1p0_modes_fast_clock,
|
|
|
- ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
|
|
|
- 3);
|
|
|
+ ar9580_1p0_modes_fast_clock);
|
|
|
} else {
|
|
|
/* mac */
|
|
|
- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
|
|
|
- ar9300_2p2_mac_core,
|
|
|
- ARRAY_SIZE(ar9300_2p2_mac_core), 2);
|
|
|
+ ar9300_2p2_mac_core);
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
|
|
|
- ar9300_2p2_mac_postamble,
|
|
|
- ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
|
|
|
+ ar9300_2p2_mac_postamble);
|
|
|
|
|
|
/* bb */
|
|
|
- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
|
|
|
- ar9300_2p2_baseband_core,
|
|
|
- ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
|
|
|
+ ar9300_2p2_baseband_core);
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
|
|
|
- ar9300_2p2_baseband_postamble,
|
|
|
- ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
|
|
|
+ ar9300_2p2_baseband_postamble);
|
|
|
|
|
|
/* radio */
|
|
|
- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
|
|
|
- ar9300_2p2_radio_core,
|
|
|
- ARRAY_SIZE(ar9300_2p2_radio_core), 2);
|
|
|
+ ar9300_2p2_radio_core);
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
|
|
|
- ar9300_2p2_radio_postamble,
|
|
|
- ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
|
|
|
+ ar9300_2p2_radio_postamble);
|
|
|
|
|
|
/* soc */
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
|
|
|
- ar9300_2p2_soc_preamble,
|
|
|
- ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
|
|
|
- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
|
|
|
+ ar9300_2p2_soc_preamble);
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
|
|
|
- ar9300_2p2_soc_postamble,
|
|
|
- ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
|
|
|
+ ar9300_2p2_soc_postamble);
|
|
|
|
|
|
/* rx/tx gain */
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9300Common_rx_gain_table_2p2,
|
|
|
- ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
|
|
|
+ ar9300Common_rx_gain_table_2p2);
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
|
|
|
- ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
|
|
|
- 5);
|
|
|
+ ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
|
|
|
|
|
|
/* Load PCIE SERDES settings from INI */
|
|
|
|
|
|
/* Awake Setting */
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
|
|
- ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
|
|
|
- ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
|
|
|
- 2);
|
|
|
+ ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
|
|
|
|
|
|
/* Sleep Setting */
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
|
|
- ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
|
|
|
- ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
|
|
|
- 2);
|
|
|
+ ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
|
|
|
|
|
|
/* Fast clock modal settings */
|
|
|
INIT_INI_ARRAY(&ah->iniModesFastClock,
|
|
|
- ar9300Modes_fast_clock_2p2,
|
|
|
- ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
|
|
|
- 3);
|
|
|
+ ar9300Modes_fast_clock_2p2);
|
|
|
}
|
|
|
}
|
|
|
|
|
@@ -507,156 +355,110 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
|
|
|
{
|
|
|
if (AR_SREV_9330_12(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9331_modes_lowest_ob_db_tx_gain_1p2,
|
|
|
- ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
|
|
|
- 5);
|
|
|
+ ar9331_modes_lowest_ob_db_tx_gain_1p2);
|
|
|
else if (AR_SREV_9330_11(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9331_modes_lowest_ob_db_tx_gain_1p1,
|
|
|
- ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
|
|
|
- 5);
|
|
|
+ ar9331_modes_lowest_ob_db_tx_gain_1p1);
|
|
|
else if (AR_SREV_9340(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
|
|
|
- ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
|
|
|
- 5);
|
|
|
+ ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
|
|
|
else if (AR_SREV_9485_11(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9485_modes_lowest_ob_db_tx_gain_1_1,
|
|
|
- ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
|
|
|
- 5);
|
|
|
+ ar9485_modes_lowest_ob_db_tx_gain_1_1);
|
|
|
else if (AR_SREV_9550(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar955x_1p0_modes_xpa_tx_gain_table,
|
|
|
- ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
|
|
|
- 9);
|
|
|
+ ar955x_1p0_modes_xpa_tx_gain_table);
|
|
|
else if (AR_SREV_9580(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9580_1p0_lowest_ob_db_tx_gain_table,
|
|
|
- ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
|
|
|
- 5);
|
|
|
+ ar9580_1p0_lowest_ob_db_tx_gain_table);
|
|
|
else if (AR_SREV_9462_20(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9462_modes_low_ob_db_tx_gain_table_2p0,
|
|
|
- ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
|
|
|
- 5);
|
|
|
+ ar9462_modes_low_ob_db_tx_gain_table_2p0);
|
|
|
else
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
|
|
|
- ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
|
|
|
- 5);
|
|
|
+ ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
|
|
|
}
|
|
|
|
|
|
static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
|
|
|
{
|
|
|
if (AR_SREV_9330_12(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9331_modes_high_ob_db_tx_gain_1p2,
|
|
|
- ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
|
|
|
- 5);
|
|
|
+ ar9331_modes_high_ob_db_tx_gain_1p2);
|
|
|
else if (AR_SREV_9330_11(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9331_modes_high_ob_db_tx_gain_1p1,
|
|
|
- ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
|
|
|
- 5);
|
|
|
+ ar9331_modes_high_ob_db_tx_gain_1p1);
|
|
|
else if (AR_SREV_9340(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
|
|
|
- ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
|
|
|
- 5);
|
|
|
+ ar9340Modes_high_ob_db_tx_gain_table_1p0);
|
|
|
else if (AR_SREV_9485_11(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9485Modes_high_ob_db_tx_gain_1_1,
|
|
|
- ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
|
|
|
- 5);
|
|
|
+ ar9485Modes_high_ob_db_tx_gain_1_1);
|
|
|
else if (AR_SREV_9580(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9580_1p0_high_ob_db_tx_gain_table,
|
|
|
- ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
|
|
|
- 5);
|
|
|
+ ar9580_1p0_high_ob_db_tx_gain_table);
|
|
|
else if (AR_SREV_9550(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar955x_1p0_modes_no_xpa_tx_gain_table,
|
|
|
- ARRAY_SIZE(ar955x_1p0_modes_no_xpa_tx_gain_table),
|
|
|
- 9);
|
|
|
+ ar955x_1p0_modes_no_xpa_tx_gain_table);
|
|
|
else if (AR_SREV_9462_20(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9462_modes_high_ob_db_tx_gain_table_2p0,
|
|
|
- ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
|
|
|
- 5);
|
|
|
+ ar9462_modes_high_ob_db_tx_gain_table_2p0);
|
|
|
else
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9300Modes_high_ob_db_tx_gain_table_2p2,
|
|
|
- ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
|
|
|
- 5);
|
|
|
+ ar9300Modes_high_ob_db_tx_gain_table_2p2);
|
|
|
}
|
|
|
|
|
|
static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
|
|
|
{
|
|
|
if (AR_SREV_9330_12(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9331_modes_low_ob_db_tx_gain_1p2,
|
|
|
- ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
|
|
|
- 5);
|
|
|
+ ar9331_modes_low_ob_db_tx_gain_1p2);
|
|
|
else if (AR_SREV_9330_11(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9331_modes_low_ob_db_tx_gain_1p1,
|
|
|
- ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
|
|
|
- 5);
|
|
|
+ ar9331_modes_low_ob_db_tx_gain_1p1);
|
|
|
else if (AR_SREV_9340(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
|
|
|
- ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
|
|
|
- 5);
|
|
|
+ ar9340Modes_low_ob_db_tx_gain_table_1p0);
|
|
|
else if (AR_SREV_9485_11(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9485Modes_low_ob_db_tx_gain_1_1,
|
|
|
- ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
|
|
|
- 5);
|
|
|
+ ar9485Modes_low_ob_db_tx_gain_1_1);
|
|
|
else if (AR_SREV_9580(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9580_1p0_low_ob_db_tx_gain_table,
|
|
|
- ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
|
|
|
- 5);
|
|
|
+ ar9580_1p0_low_ob_db_tx_gain_table);
|
|
|
else
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9300Modes_low_ob_db_tx_gain_table_2p2,
|
|
|
- ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
|
|
|
- 5);
|
|
|
+ ar9300Modes_low_ob_db_tx_gain_table_2p2);
|
|
|
}
|
|
|
|
|
|
static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
|
|
|
{
|
|
|
if (AR_SREV_9330_12(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9331_modes_high_power_tx_gain_1p2,
|
|
|
- ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
|
|
|
- 5);
|
|
|
+ ar9331_modes_high_power_tx_gain_1p2);
|
|
|
else if (AR_SREV_9330_11(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9331_modes_high_power_tx_gain_1p1,
|
|
|
- ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
|
|
|
- 5);
|
|
|
+ ar9331_modes_high_power_tx_gain_1p1);
|
|
|
else if (AR_SREV_9340(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
|
|
|
- ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
|
|
|
- 5);
|
|
|
+ ar9340Modes_high_power_tx_gain_table_1p0);
|
|
|
else if (AR_SREV_9485_11(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9485Modes_high_power_tx_gain_1_1,
|
|
|
- ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
|
|
|
- 5);
|
|
|
+ ar9485Modes_high_power_tx_gain_1_1);
|
|
|
else if (AR_SREV_9580(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9580_1p0_high_power_tx_gain_table,
|
|
|
- ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
|
|
|
- 5);
|
|
|
+ ar9580_1p0_high_power_tx_gain_table);
|
|
|
else
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
- ar9300Modes_high_power_tx_gain_table_2p2,
|
|
|
- ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
|
|
|
- 5);
|
|
|
+ ar9300Modes_high_power_tx_gain_table_2p2);
|
|
|
+}
|
|
|
+
|
|
|
+static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
|
|
|
+{
|
|
|
+ if (AR_SREV_9340(ah))
|
|
|
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
+ ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
|
|
|
+ else if (AR_SREV_9580(ah))
|
|
|
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
+ ar9580_1p0_mixed_ob_db_tx_gain_table);
|
|
|
}
|
|
|
|
|
|
static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
|
|
@@ -675,6 +477,9 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
|
|
|
case 3:
|
|
|
ar9003_tx_gain_table_mode3(ah);
|
|
|
break;
|
|
|
+ case 4:
|
|
|
+ ar9003_tx_gain_table_mode4(ah);
|
|
|
+ break;
|
|
|
}
|
|
|
}
|
|
|
|
|
@@ -682,104 +487,67 @@ static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
|
|
|
{
|
|
|
if (AR_SREV_9330_12(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9331_common_rx_gain_1p2,
|
|
|
- ARRAY_SIZE(ar9331_common_rx_gain_1p2),
|
|
|
- 2);
|
|
|
+ ar9331_common_rx_gain_1p2);
|
|
|
else if (AR_SREV_9330_11(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9331_common_rx_gain_1p1,
|
|
|
- ARRAY_SIZE(ar9331_common_rx_gain_1p1),
|
|
|
- 2);
|
|
|
+ ar9331_common_rx_gain_1p1);
|
|
|
else if (AR_SREV_9340(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9340Common_rx_gain_table_1p0,
|
|
|
- ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
|
|
|
- 2);
|
|
|
+ ar9340Common_rx_gain_table_1p0);
|
|
|
else if (AR_SREV_9485_11(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9485Common_wo_xlna_rx_gain_1_1,
|
|
|
- ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
|
|
|
- 2);
|
|
|
+ ar9485Common_wo_xlna_rx_gain_1_1);
|
|
|
else if (AR_SREV_9550(ah)) {
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar955x_1p0_common_rx_gain_table,
|
|
|
- ARRAY_SIZE(ar955x_1p0_common_rx_gain_table),
|
|
|
- 2);
|
|
|
+ ar955x_1p0_common_rx_gain_table);
|
|
|
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
|
|
|
- ar955x_1p0_common_rx_gain_bounds,
|
|
|
- ARRAY_SIZE(ar955x_1p0_common_rx_gain_bounds),
|
|
|
- 5);
|
|
|
+ ar955x_1p0_common_rx_gain_bounds);
|
|
|
} else if (AR_SREV_9580(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9580_1p0_rx_gain_table,
|
|
|
- ARRAY_SIZE(ar9580_1p0_rx_gain_table),
|
|
|
- 2);
|
|
|
+ ar9580_1p0_rx_gain_table);
|
|
|
else if (AR_SREV_9462_20(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9462_common_rx_gain_table_2p0,
|
|
|
- ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
|
|
|
- 2);
|
|
|
+ ar9462_common_rx_gain_table_2p0);
|
|
|
else
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9300Common_rx_gain_table_2p2,
|
|
|
- ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
|
|
|
- 2);
|
|
|
+ ar9300Common_rx_gain_table_2p2);
|
|
|
}
|
|
|
|
|
|
static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
|
|
|
{
|
|
|
if (AR_SREV_9330_12(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9331_common_wo_xlna_rx_gain_1p2,
|
|
|
- ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
|
|
|
- 2);
|
|
|
+ ar9331_common_wo_xlna_rx_gain_1p2);
|
|
|
else if (AR_SREV_9330_11(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9331_common_wo_xlna_rx_gain_1p1,
|
|
|
- ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
|
|
|
- 2);
|
|
|
+ ar9331_common_wo_xlna_rx_gain_1p1);
|
|
|
else if (AR_SREV_9340(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9340Common_wo_xlna_rx_gain_table_1p0,
|
|
|
- ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
|
|
|
- 2);
|
|
|
+ ar9340Common_wo_xlna_rx_gain_table_1p0);
|
|
|
else if (AR_SREV_9485_11(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9485Common_wo_xlna_rx_gain_1_1,
|
|
|
- ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
|
|
|
- 2);
|
|
|
+ ar9485Common_wo_xlna_rx_gain_1_1);
|
|
|
else if (AR_SREV_9462_20(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9462_common_wo_xlna_rx_gain_table_2p0,
|
|
|
- ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
|
|
|
- 2);
|
|
|
+ ar9462_common_wo_xlna_rx_gain_table_2p0);
|
|
|
else if (AR_SREV_9550(ah)) {
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar955x_1p0_common_wo_xlna_rx_gain_table,
|
|
|
- ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
|
|
|
- 2);
|
|
|
+ ar955x_1p0_common_wo_xlna_rx_gain_table);
|
|
|
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
|
|
|
- ar955x_1p0_common_wo_xlna_rx_gain_bounds,
|
|
|
- ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
|
|
|
- 5);
|
|
|
+ ar955x_1p0_common_wo_xlna_rx_gain_bounds);
|
|
|
} else if (AR_SREV_9580(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9580_1p0_wo_xlna_rx_gain_table,
|
|
|
- ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
|
|
|
- 2);
|
|
|
+ ar9580_1p0_wo_xlna_rx_gain_table);
|
|
|
else
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9300Common_wo_xlna_rx_gain_table_2p2,
|
|
|
- ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
|
|
|
- 2);
|
|
|
+ ar9300Common_wo_xlna_rx_gain_table_2p2);
|
|
|
}
|
|
|
|
|
|
static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
|
|
|
{
|
|
|
if (AR_SREV_9462_20(ah))
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
- ar9462_common_mixed_rx_gain_table_2p0,
|
|
|
- ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
|
|
|
+ ar9462_common_mixed_rx_gain_table_2p0);
|
|
|
}
|
|
|
|
|
|
static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
|