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powerpc/86xx: Support for NVRAM on GE Fanuc's SBC310

Add support for NVRAM on GE Fanuc's SBC310.

Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Martyn Welch 16 lat temu
rodzic
commit
9093067ad1

+ 6 - 0
arch/powerpc/boot/dts/gef_sbc310.dts

@@ -115,6 +115,12 @@
 			};
 			};
 		};
 		};
 
 
+		nvram@3,0 {
+			device_type = "nvram";
+			compatible = "simtek,stk14ca8";
+			reg = <0x3 0x0 0x20000>;
+		};
+
 		fpga@4,0 {
 		fpga@4,0 {
 			compatible = "gef,fpga-regs";
 			compatible = "gef,fpga-regs";
 			reg = <0x4 0x0 0x40>;
 			reg = <0x4 0x0 0x40>;

+ 1 - 1
arch/powerpc/configs/86xx/gef_sbc310_defconfig

@@ -218,7 +218,7 @@ CONFIG_MPIC=y
 # CONFIG_MPIC_WEIRD is not set
 # CONFIG_MPIC_WEIRD is not set
 # CONFIG_PPC_I8259 is not set
 # CONFIG_PPC_I8259 is not set
 # CONFIG_PPC_RTAS is not set
 # CONFIG_PPC_RTAS is not set
-# CONFIG_MMIO_NVRAM is not set
+CONFIG_MMIO_NVRAM=y
 # CONFIG_PPC_MPC106 is not set
 # CONFIG_PPC_MPC106 is not set
 # CONFIG_PPC_970_NAP is not set
 # CONFIG_PPC_970_NAP is not set
 # CONFIG_PPC_INDIRECT_IO is not set
 # CONFIG_PPC_INDIRECT_IO is not set

+ 1 - 0
arch/powerpc/platforms/86xx/Kconfig

@@ -43,6 +43,7 @@ config GEF_PPC9A
 config GEF_SBC310
 config GEF_SBC310
 	bool "GE Fanuc SBC310"
 	bool "GE Fanuc SBC310"
 	select DEFAULT_UIMAGE
 	select DEFAULT_UIMAGE
+	select MMIO_NVRAM
 	select GENERIC_GPIO
 	select GENERIC_GPIO
 	select ARCH_REQUIRE_GPIOLIB
 	select ARCH_REQUIRE_GPIOLIB
 	help
 	help

+ 5 - 0
arch/powerpc/platforms/86xx/gef_sbc310.c

@@ -33,6 +33,7 @@
 #include <asm/udbg.h>
 #include <asm/udbg.h>
 
 
 #include <asm/mpic.h>
 #include <asm/mpic.h>
+#include <asm/nvram.h>
 
 
 #include <sysdev/fsl_pci.h>
 #include <sysdev/fsl_pci.h>
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_soc.h>
@@ -95,6 +96,10 @@ static void __init gef_sbc310_setup_arch(void)
 			printk(KERN_WARNING "Unable to map board registers\n");
 			printk(KERN_WARNING "Unable to map board registers\n");
 		of_node_put(regs);
 		of_node_put(regs);
 	}
 	}
+
+#if defined(CONFIG_MMIO_NVRAM)
+	mmio_nvram_init();
+#endif
 }
 }
 
 
 /* Return the PCB revision */
 /* Return the PCB revision */