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@@ -818,20 +818,22 @@ int i915_save_state(struct drm_device *dev)
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i915_save_display(dev);
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- /* Interrupt state */
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- if (HAS_PCH_SPLIT(dev)) {
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- dev_priv->saveDEIER = I915_READ(DEIER);
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- dev_priv->saveDEIMR = I915_READ(DEIMR);
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- dev_priv->saveGTIER = I915_READ(GTIER);
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- dev_priv->saveGTIMR = I915_READ(GTIMR);
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- dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
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- dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
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- dev_priv->saveMCHBAR_RENDER_STANDBY =
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- I915_READ(RSTDBYCTL);
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- dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
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- } else {
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- dev_priv->saveIER = I915_READ(IER);
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- dev_priv->saveIMR = I915_READ(IMR);
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+ if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
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+ /* Interrupt state */
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+ if (HAS_PCH_SPLIT(dev)) {
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+ dev_priv->saveDEIER = I915_READ(DEIER);
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+ dev_priv->saveDEIMR = I915_READ(DEIMR);
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+ dev_priv->saveGTIER = I915_READ(GTIER);
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+ dev_priv->saveGTIMR = I915_READ(GTIMR);
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+ dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
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+ dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
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+ dev_priv->saveMCHBAR_RENDER_STANDBY =
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+ I915_READ(RSTDBYCTL);
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+ dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
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+ } else {
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+ dev_priv->saveIER = I915_READ(IER);
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+ dev_priv->saveIMR = I915_READ(IMR);
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+ }
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}
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intel_disable_gt_powersave(dev);
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@@ -869,18 +871,20 @@ int i915_restore_state(struct drm_device *dev)
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i915_restore_display(dev);
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- /* Interrupt state */
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- if (HAS_PCH_SPLIT(dev)) {
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- I915_WRITE(DEIER, dev_priv->saveDEIER);
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- I915_WRITE(DEIMR, dev_priv->saveDEIMR);
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- I915_WRITE(GTIER, dev_priv->saveGTIER);
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- I915_WRITE(GTIMR, dev_priv->saveGTIMR);
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- I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
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- I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
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- I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->savePCH_PORT_HOTPLUG);
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- } else {
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- I915_WRITE(IER, dev_priv->saveIER);
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- I915_WRITE(IMR, dev_priv->saveIMR);
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+ if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
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+ /* Interrupt state */
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+ if (HAS_PCH_SPLIT(dev)) {
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+ I915_WRITE(DEIER, dev_priv->saveDEIER);
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+ I915_WRITE(DEIMR, dev_priv->saveDEIMR);
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+ I915_WRITE(GTIER, dev_priv->saveGTIER);
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+ I915_WRITE(GTIMR, dev_priv->saveGTIMR);
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+ I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
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+ I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
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+ I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->savePCH_PORT_HOTPLUG);
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+ } else {
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+ I915_WRITE(IER, dev_priv->saveIER);
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+ I915_WRITE(IMR, dev_priv->saveIMR);
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+ }
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}
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/* Cache mode state */
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