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@@ -2033,6 +2033,33 @@ static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
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.class = &omap2_hdq1w_class,
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};
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+/* SAD2D */
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+static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
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+ { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
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+ { .name = "rst_modem_sw", .rst_shift = 1 },
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+};
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+
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+static struct omap_hwmod_class omap3xxx_sad2d_class = {
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+ .name = "sad2d",
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+};
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+
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+static struct omap_hwmod omap3xxx_sad2d_hwmod = {
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+ .name = "sad2d",
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+ .rst_lines = omap3xxx_sad2d_resets,
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+ .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets),
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+ .main_clk = "sad2d_ick",
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+ .prcm = {
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+ .omap2 = {
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+ .module_offs = CORE_MOD,
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+ .prcm_reg_id = 1,
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+ .module_bit = OMAP3430_EN_SAD2D_SHIFT,
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+ .idlest_reg_id = 1,
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+ .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
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+ },
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+ },
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+ .class = &omap3xxx_sad2d_class,
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+};
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+
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/*
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* '32K sync counter' class
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* 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
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@@ -2137,6 +2164,14 @@ static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
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.user = OCP_USER_MPU,
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};
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+/* l3_core -> sad2d interface */
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+static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
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+ .master = &omap3xxx_sad2d_hwmod,
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+ .slave = &omap3xxx_l3_main_hwmod,
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+ .clk = "core_l3_ick",
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+ .user = OCP_USER_MPU,
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+};
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+
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/* L4_CORE -> L4_WKUP interface */
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static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
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.master = &omap3xxx_l4_core_hwmod,
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@@ -3371,6 +3406,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
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&omap34xx_l4_core__sr2,
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&omap3xxx_l4_core__mailbox,
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&omap3xxx_l4_core__hdq1w,
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+ &omap3xxx_sad2d__l3,
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NULL
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};
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@@ -3391,6 +3427,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
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&omap3xxx_l4_core__es3plus_mmc1,
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&omap3xxx_l4_core__es3plus_mmc2,
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&omap3xxx_l4_core__hdq1w,
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+ &omap3xxx_sad2d__l3,
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NULL
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};
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