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@@ -1958,7 +1958,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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enum port port = dp_to_dig_port(intel_dp)->port;
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- if (IS_VALLEYVIEW(dev))
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+ if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
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return DP_TRAIN_VOLTAGE_SWING_1200;
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else if (IS_GEN7(dev) && port == PORT_A)
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return DP_TRAIN_VOLTAGE_SWING_800;
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@@ -1974,7 +1974,18 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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enum port port = dp_to_dig_port(intel_dp)->port;
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- if (HAS_DDI(dev)) {
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+ if (IS_BROADWELL(dev)) {
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+ switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
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+ case DP_TRAIN_VOLTAGE_SWING_400:
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+ case DP_TRAIN_VOLTAGE_SWING_600:
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+ return DP_TRAIN_PRE_EMPHASIS_6;
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+ case DP_TRAIN_VOLTAGE_SWING_800:
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+ return DP_TRAIN_PRE_EMPHASIS_3_5;
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+ case DP_TRAIN_VOLTAGE_SWING_1200:
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+ default:
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+ return DP_TRAIN_PRE_EMPHASIS_0;
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+ }
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+ } else if (IS_HASWELL(dev)) {
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switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_400:
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return DP_TRAIN_PRE_EMPHASIS_9_5;
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@@ -2286,6 +2297,41 @@ intel_hsw_signal_levels(uint8_t train_set)
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}
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}
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+static uint32_t
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+intel_bdw_signal_levels(uint8_t train_set)
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+{
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+ int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
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+ DP_TRAIN_PRE_EMPHASIS_MASK);
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+ switch (signal_levels) {
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+ case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
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+ return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
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+ case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
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+ return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
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+ case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
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+ return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
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+
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+ case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
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+ return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
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+ case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
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+ return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
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+ case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
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+ return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
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+
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+ case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
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+ return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
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+ case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
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+ return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
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+
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+ case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
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+ return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
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+
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+ default:
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+ DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
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+ "0x%x\n", signal_levels);
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+ return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
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+ }
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+}
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+
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/* Properly updates "DP" with the correct signal levels. */
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static void
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intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
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@@ -2296,7 +2342,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
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uint32_t signal_levels, mask;
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uint8_t train_set = intel_dp->train_set[0];
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- if (HAS_DDI(dev)) {
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+ if (IS_BROADWELL(dev)) {
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+ signal_levels = intel_bdw_signal_levels(train_set);
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+ mask = DDI_BUF_EMP_MASK;
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+ } else if (IS_HASWELL(dev)) {
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signal_levels = intel_hsw_signal_levels(train_set);
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mask = DDI_BUF_EMP_MASK;
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} else if (IS_VALLEYVIEW(dev)) {
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