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@@ -88,7 +88,7 @@ static void print_pll(struct device *dev, struct smiapp_pll *pll)
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}
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static int __smiapp_pll_calculate(struct device *dev,
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- struct smiapp_pll_limits *limits,
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+ const struct smiapp_pll_limits *limits,
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struct smiapp_pll *pll, uint32_t mul,
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uint32_t div, uint32_t lane_op_clock_ratio)
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{
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@@ -306,14 +306,10 @@ static int __smiapp_pll_calculate(struct device *dev,
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pll->pixel_rate_csi =
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pll->op_pix_clk_freq_hz * lane_op_clock_ratio;
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- rval = bounds_check(dev, pll->pre_pll_clk_div,
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- limits->min_pre_pll_clk_div,
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- limits->max_pre_pll_clk_div, "pre_pll_clk_div");
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- if (!rval)
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- rval = bounds_check(
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- dev, pll->pll_ip_clk_freq_hz,
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- limits->min_pll_ip_freq_hz, limits->max_pll_ip_freq_hz,
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- "pll_ip_clk_freq_hz");
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+ rval = bounds_check(dev, pll->pll_ip_clk_freq_hz,
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+ limits->min_pll_ip_freq_hz,
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+ limits->max_pll_ip_freq_hz,
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+ "pll_ip_clk_freq_hz");
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if (!rval)
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rval = bounds_check(
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dev, pll->pll_multiplier,
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@@ -362,9 +358,12 @@ static int __smiapp_pll_calculate(struct device *dev,
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return rval;
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}
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-int smiapp_pll_calculate(struct device *dev, struct smiapp_pll_limits *limits,
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+int smiapp_pll_calculate(struct device *dev,
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+ const struct smiapp_pll_limits *limits,
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struct smiapp_pll *pll)
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{
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+ uint16_t min_pre_pll_clk_div;
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+ uint16_t max_pre_pll_clk_div;
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uint32_t lane_op_clock_ratio;
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uint32_t mul, div;
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unsigned int i;
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@@ -397,33 +396,33 @@ int smiapp_pll_calculate(struct device *dev, struct smiapp_pll_limits *limits,
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/* Figure out limits for pre-pll divider based on extclk */
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dev_dbg(dev, "min / max pre_pll_clk_div: %d / %d\n",
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limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
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- limits->max_pre_pll_clk_div =
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+ max_pre_pll_clk_div =
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min_t(uint16_t, limits->max_pre_pll_clk_div,
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clk_div_even(pll->ext_clk_freq_hz /
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limits->min_pll_ip_freq_hz));
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- limits->min_pre_pll_clk_div =
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+ min_pre_pll_clk_div =
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max_t(uint16_t, limits->min_pre_pll_clk_div,
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clk_div_even_up(
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DIV_ROUND_UP(pll->ext_clk_freq_hz,
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limits->max_pll_ip_freq_hz)));
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dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %d / %d\n",
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- limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
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+ min_pre_pll_clk_div, max_pre_pll_clk_div);
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i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
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mul = div_u64(pll->pll_op_clk_freq_hz, i);
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div = pll->ext_clk_freq_hz / i;
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dev_dbg(dev, "mul %d / div %d\n", mul, div);
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- limits->min_pre_pll_clk_div =
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- max_t(uint16_t, limits->min_pre_pll_clk_div,
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+ min_pre_pll_clk_div =
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+ max_t(uint16_t, min_pre_pll_clk_div,
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clk_div_even_up(
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DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
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limits->max_pll_op_freq_hz)));
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dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %d / %d\n",
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- limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
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+ min_pre_pll_clk_div, max_pre_pll_clk_div);
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- for (pll->pre_pll_clk_div = limits->min_pre_pll_clk_div;
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- pll->pre_pll_clk_div <= limits->max_pre_pll_clk_div;
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+ for (pll->pre_pll_clk_div = min_pre_pll_clk_div;
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+ pll->pre_pll_clk_div <= max_pre_pll_clk_div;
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pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) {
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rval = __smiapp_pll_calculate(dev, limits, pll, mul, div,
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lane_op_clock_ratio);
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