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@@ -616,11 +616,22 @@ static void cayman_gpu_init(struct radeon_device *rdev)
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WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
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WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
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- tmp = gb_addr_config & NUM_PIPES_MASK;
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- tmp = r6xx_remap_render_backend(rdev, tmp,
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- rdev->config.cayman.max_backends_per_se *
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- rdev->config.cayman.max_shader_engines,
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- CAYMAN_MAX_BACKENDS, disabled_rb_mask);
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+ if ((rdev->config.cayman.max_backends_per_se == 1) &&
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+ (rdev->flags & RADEON_IS_IGP)) {
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+ if ((disabled_rb_mask & 3) == 1) {
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+ /* RB0 disabled, RB1 enabled */
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+ tmp = 0x11111111;
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+ } else {
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+ /* RB1 disabled, RB0 enabled */
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+ tmp = 0x00000000;
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+ }
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+ } else {
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+ tmp = gb_addr_config & NUM_PIPES_MASK;
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+ tmp = r6xx_remap_render_backend(rdev, tmp,
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+ rdev->config.cayman.max_backends_per_se *
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+ rdev->config.cayman.max_shader_engines,
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+ CAYMAN_MAX_BACKENDS, disabled_rb_mask);
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+ }
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WREG32(GB_BACKEND_MAP, tmp);
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cgts_tcc_disable = 0xffff0000;
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