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@@ -1190,12 +1190,12 @@ int xhci_endpoint_init(struct xhci_hcd *xhci,
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/* FIXME dig Mult and streams info out of ep companion desc */
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/* Allow 3 retries for everything but isoc;
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- * error count = 0 means infinite retries.
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+ * CErr shall be set to 0 for Isoch endpoints.
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*/
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if (!usb_endpoint_xfer_isoc(&ep->desc))
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ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
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else
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- ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(1));
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+ ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
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ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
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@@ -1246,8 +1246,15 @@ int xhci_endpoint_init(struct xhci_hcd *xhci,
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* including link TRBs, No-op TRBs, and Event data TRBs. Since we don't
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* use Event Data TRBs, and we don't chain in a link TRB on short
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* transfers, we're basically dividing by 1.
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+ *
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+ * xHCI 1.0 specification indicates that the Average TRB Length should
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+ * be set to 8 for control endpoints.
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*/
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- ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
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+ if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
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+ ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
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+ else
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+ ep_ctx->tx_info |=
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+ cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
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/* FIXME Debug endpoint context */
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return 0;
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