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@@ -1,13 +1,13 @@
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-/* arch/arm/plat-samsung/include/plat/regs-fb.h
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+/* include/video/samsung_fimd.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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- * S3C Platform - new-style framebuffer register definitions
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+ * S3C Platform - new-style fimd and framebuffer register definitions
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*
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- * This is the register set for the new style framebuffer interface
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+ * This is the register set for the fimd and new style framebuffer interface
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* found from the S3C2443 onwards into the S3C2416, S3C2450 and the
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* S3C64XX series such as the S3C6400 and S3C6410.
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*
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@@ -15,19 +15,11 @@
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* whichever architecture is selected, it only contains the core of the
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* register set. See <mach/regs-fb.h> to get the specifics.
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*
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- * Note, we changed to using regs-fb.h as it avoids any clashes with
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- * the original regs-lcd.h so out of the way of regs-lcd.h as well as
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- * indicating the newer block is much more than just an LCD interface.
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- *
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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-/* Please do not include this file directly, use <mach/regs-fb.h> to
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- * ensure all the localised SoC support is included as necessary.
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-*/
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-
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/* VIDCON0 */
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#define VIDCON0 (0x00)
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@@ -401,3 +393,141 @@
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#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
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#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
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+#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
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+#define VIDCON1_FSTATUS_EVEN (1 << 15)
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+
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+/* Video timing controls */
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+#define VIDTCON0 (0x10)
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+#define VIDTCON1 (0x14)
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+#define VIDTCON2 (0x18)
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+
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+/* Window position controls */
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+
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+#define WINCON(_win) (0x20 + ((_win) * 4))
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+
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+/* OSD1 and OSD4 do not have register D */
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+
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+#define VIDOSD_BASE (0x40)
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+
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+#define VIDINTCON0 (0x130)
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+
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+/* WINCONx */
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+
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+#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
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+#define WINCONx_CSCWIDTH_SHIFT (26)
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+#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
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+#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
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+
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+#define WINCONx_ENLOCAL (1 << 22)
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+#define WINCONx_BUFSTATUS (1 << 21)
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+#define WINCONx_BUFSEL (1 << 20)
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+#define WINCONx_BUFAUTOEN (1 << 19)
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+#define WINCONx_YCbCr (1 << 13)
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+
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+#define WINCON1_LOCALSEL_CAMIF (1 << 23)
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+
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+#define WINCON2_LOCALSEL_CAMIF (1 << 23)
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+#define WINCON2_BLD_PIX (1 << 6)
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+
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+#define WINCON2_ALPHA_SEL (1 << 1)
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+#define WINCON2_BPPMODE_MASK (0xf << 2)
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+#define WINCON2_BPPMODE_SHIFT (2)
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+#define WINCON2_BPPMODE_1BPP (0x0 << 2)
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+#define WINCON2_BPPMODE_2BPP (0x1 << 2)
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+#define WINCON2_BPPMODE_4BPP (0x2 << 2)
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+#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
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+#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
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+#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
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+#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
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+#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
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+#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
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+#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
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+#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
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+#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
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+#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
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+#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
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+
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+#define WINCON3_BLD_PIX (1 << 6)
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+
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+#define WINCON3_ALPHA_SEL (1 << 1)
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+#define WINCON3_BPPMODE_MASK (0xf << 2)
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+#define WINCON3_BPPMODE_SHIFT (2)
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+#define WINCON3_BPPMODE_1BPP (0x0 << 2)
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+#define WINCON3_BPPMODE_2BPP (0x1 << 2)
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+#define WINCON3_BPPMODE_4BPP (0x2 << 2)
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+#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
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+#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
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+#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
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+#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
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+#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
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+#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
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+#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
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+#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
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+#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
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+#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
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+
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+#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
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+#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
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+#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
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+
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+#define DITHMODE (0x170)
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+#define WINxMAP(_win) (0x180 + ((_win) * 4))
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+
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+
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+#define DITHMODE_R_POS_MASK (0x3 << 5)
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+#define DITHMODE_R_POS_SHIFT (5)
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+#define DITHMODE_R_POS_8BIT (0x0 << 5)
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+#define DITHMODE_R_POS_6BIT (0x1 << 5)
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+#define DITHMODE_R_POS_5BIT (0x2 << 5)
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+
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+#define DITHMODE_G_POS_MASK (0x3 << 3)
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+#define DITHMODE_G_POS_SHIFT (3)
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+#define DITHMODE_G_POS_8BIT (0x0 << 3)
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+#define DITHMODE_G_POS_6BIT (0x1 << 3)
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+#define DITHMODE_G_POS_5BIT (0x2 << 3)
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+
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+#define DITHMODE_B_POS_MASK (0x3 << 1)
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+#define DITHMODE_B_POS_SHIFT (1)
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+#define DITHMODE_B_POS_8BIT (0x0 << 1)
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+#define DITHMODE_B_POS_6BIT (0x1 << 1)
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+#define DITHMODE_B_POS_5BIT (0x2 << 1)
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+
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+#define DITHMODE_DITH_EN (1 << 0)
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+
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+#define WPALCON (0x1A0)
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+
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+/* Palette control */
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+/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
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+ * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
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+#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
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+#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
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+#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
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+
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+
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+/* Notes on per-window bpp settings
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+ *
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+ * Value Win0 Win1 Win2 Win3 Win 4
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+ * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
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+ * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
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+ * 0010 4(P) 4(P) 4(P) 4(P) -none-
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+ * 0011 8(P) 8(P) -none- -none- -none-
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+ * 0100 -none- 8(A232) 8(A232) -none- -none-
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+ * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
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+ * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
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+ * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
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+ * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
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+ * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
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+ * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
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+ * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
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+ * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
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+ * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
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+ * 1110 -none- -none- -none- -none- -none-
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+ * 1111 -none- -none- -none- -none- -none-
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+*/
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+
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+/* FIMD Version 8 register offset definitions */
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+#define FIMD_V8_VIDTCON0 (0x20010)
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+#define FIMD_V8_VIDTCON1 (0x20014)
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+#define FIMD_V8_VIDTCON2 (0x20018)
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+#define FIMD_V8_VIDTCON3 (0x2001C)
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+#define FIMD_V8_VIDCON1 (0x20004)
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