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@@ -19,13 +19,16 @@
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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+#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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-#include <mach/common.h>
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+#include <linux/platform_data/irq-renesas-intc-irqpin.h>
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#include <linux/irqchip.h>
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+#include <mach/common.h>
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#include <mach/intc.h>
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+#include <mach/irqs.h>
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#include <mach/r8a7779.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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@@ -39,6 +42,54 @@
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#define INT2NTSR0 IOMEM(0xfe700060)
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#define INT2NTSR1 IOMEM(0xfe700064)
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+struct renesas_intc_irqpin_config irqpin0_platform_data = {
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+ .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
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+ .sense_bitfield_width = 2,
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+};
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+
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+static struct resource irqpin0_resources[] = {
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+ DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
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+ DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
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+ DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
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+ DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
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+ DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
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+ DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
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+ DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
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+ DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
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+ DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
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+};
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+
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+static struct platform_device irqpin0_device = {
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+ .name = "renesas_intc_irqpin",
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+ .id = 0,
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+ .resource = irqpin0_resources,
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+ .num_resources = ARRAY_SIZE(irqpin0_resources),
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+ .dev = {
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+ .platform_data = &irqpin0_platform_data,
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+ },
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+};
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+
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+void __init r8a7779_init_irq_extpin(int irlm)
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+{
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+ void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
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+ unsigned long tmp;
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+
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+ if (icr0) {
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+ tmp = ioread32(icr0);
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+ if (irlm)
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+ tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
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+ else
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+ tmp &= ~(1 << 23); /* IRL mode - not supported */
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+ tmp |= (1 << 21); /* LVLMODE = 1 */
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+ iowrite32(tmp, icr0);
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+ iounmap(icr0);
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+
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+ if (irlm)
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+ platform_device_register(&irqpin0_device);
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+ } else
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+ pr_warn("r8a7779: unable to setup external irq pin mode\n");
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+}
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+
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static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
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{
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return 0; /* always allow wakeup */
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