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@@ -293,12 +293,24 @@ int w1_reset_bus(struct w1_master *dev)
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result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1;
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else {
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dev->bus_master->write_bit(dev->bus_master->data, 0);
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+ /* minimum 480, max ? us
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+ * be nice and sleep, except 18b20 spec lists 960us maximum,
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+ * so until we can sleep with microsecond accuracy, spin.
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+ * Feel free to come up with some other way to give up the
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+ * cpu for such a short amount of time AND get it back in
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+ * the maximum amount of time.
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+ */
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w1_delay(480);
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dev->bus_master->write_bit(dev->bus_master->data, 1);
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w1_delay(70);
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result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1;
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- w1_delay(410);
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+ /* minmum 70 (above) + 410 = 480 us
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+ * There aren't any timing requirements between a reset and
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+ * the following transactions. Sleeping is safe here.
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+ */
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+ /* w1_delay(410); min required time */
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+ msleep(1);
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}
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return result;
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