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@@ -54,16 +54,12 @@
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#define SPIFMT_WDELAY_SHIFT 24
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#define SPIFMT_CHARLEN_MASK 0x0000001Fu
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-/* SPIGCR1 */
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-#define SPIGCR1_SPIENA_MASK 0x01000000u
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/* SPIPC0 */
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#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
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#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
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#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
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#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
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-#define SPIPC0_EN1FUN_MASK BIT(1)
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-#define SPIPC0_EN0FUN_MASK BIT(0)
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#define SPIINT_MASKALL 0x0101035F
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#define SPI_INTLVL_1 0x000001FFu
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@@ -75,6 +71,7 @@
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#define SPIGCR1_CLKMOD_MASK BIT(1)
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#define SPIGCR1_MASTER_MASK BIT(0)
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#define SPIGCR1_LOOPBACK_MASK BIT(16)
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+#define SPIGCR1_SPIENA_MASK BIT(24)
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/* SPIBUF */
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#define SPIBUF_TXFULL_MASK BIT(29)
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@@ -90,23 +87,12 @@
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#define SPIFLG_RX_INTR_MASK BIT(8)
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#define SPIFLG_TX_INTR_MASK BIT(9)
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#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
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-#define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \
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- | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
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- | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
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- | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \
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- | SPIFLG_TX_INTR_MASK \
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- | SPIFLG_BUF_INIT_ACTIVE_MASK)
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-
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-#define SPIINT_DLEN_ERR_INTR BIT(0)
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-#define SPIINT_TIMEOUT_INTR BIT(1)
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-#define SPIINT_PARERR_INTR BIT(2)
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-#define SPIINT_DESYNC_INTR BIT(3)
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+
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#define SPIINT_BITERR_INTR BIT(4)
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#define SPIINT_OVRRUN_INTR BIT(6)
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#define SPIINT_RX_INTR BIT(8)
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#define SPIINT_TX_INTR BIT(9)
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#define SPIINT_DMA_REQ_EN BIT(16)
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-#define SPIINT_ENABLE_HIGHZ BIT(24)
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#define SPI_T2CDELAY_SHIFT 16
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#define SPI_C2TDELAY_SHIFT 24
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@@ -118,26 +104,11 @@
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#define SPILVL 0x0c
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#define SPIFLG 0x10
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#define SPIPC0 0x14
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-#define SPIPC1 0x18
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-#define SPIPC2 0x1c
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-#define SPIPC3 0x20
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-#define SPIPC4 0x24
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-#define SPIPC5 0x28
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-#define SPIPC6 0x2c
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-#define SPIPC7 0x30
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-#define SPIPC8 0x34
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-#define SPIDAT0 0x38
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#define SPIDAT1 0x3c
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#define SPIBUF 0x40
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-#define SPIEMU 0x44
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#define SPIDELAY 0x48
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#define SPIDEF 0x4c
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#define SPIFMT0 0x50
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-#define SPIFMT1 0x54
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-#define SPIFMT2 0x58
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-#define SPIFMT3 0x5c
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-#define TGINTVEC0 0x60
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-#define TGINTVEC1 0x64
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struct davinci_spi_slave {
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u32 cmd_to_write;
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