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@@ -677,17 +677,15 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
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/* Flush Rx MAC FIFO on any flow control or error */
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sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
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- /* Set threshold to 0xa (64 bytes)
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- * ASF disabled so no need to do WA dev #4.30
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- */
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- sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
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+ /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
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+ sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
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/* Configure Tx MAC FIFO */
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sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
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sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
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if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
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- sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 512/8);
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+ sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
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sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
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if (hw->dev[port]->mtu > ETH_DATA_LEN) {
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/* set Tx GMAC FIFO Almost Empty Threshold */
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@@ -1061,7 +1059,8 @@ static int sky2_rx_start(struct sky2_port *sky2)
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sky2->rx_put = sky2->rx_next = 0;
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sky2_qset(hw, rxq);
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- if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
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+ if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
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+ (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) {
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/* MAC Rx RAM Read is controlled by hardware */
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sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
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}
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@@ -1510,7 +1509,7 @@ static int sky2_down(struct net_device *dev)
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/* WA for dev. #4.209 */
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if (hw->chip_id == CHIP_ID_YUKON_EC_U
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- && hw->chip_rev == CHIP_REV_YU_EC_U_A1)
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+ && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
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sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
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sky2->speed != SPEED_1000 ?
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TX_STFW_ENA : TX_STFW_DIS);
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