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@@ -4755,8 +4755,36 @@ e1000_rar_set(struct e1000_hw *hw,
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rar_low = ((uint32_t) addr[0] |
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((uint32_t) addr[1] << 8) |
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((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
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+ rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
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- rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
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+ /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
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+ * unit hang.
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+ *
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+ * Description:
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+ * If there are any Rx frames queued up or otherwise present in the HW
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+ * before RSS is enabled, and then we enable RSS, the HW Rx unit will
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+ * hang. To work around this issue, we have to disable receives and
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+ * flush out all Rx frames before we enable RSS. To do so, we modify we
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+ * redirect all Rx traffic to manageability and then reset the HW.
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+ * This flushes away Rx frames, and (since the redirections to
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+ * manageability persists across resets) keeps new ones from coming in
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+ * while we work. Then, we clear the Address Valid AV bit for all MAC
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+ * addresses and undo the re-direction to manageability.
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+ * Now, frames are coming in again, but the MAC won't accept them, so
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+ * far so good. We now proceed to initialize RSS (if necessary) and
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+ * configure the Rx unit. Last, we re-enable the AV bits and continue
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+ * on our merry way.
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+ */
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+ switch (hw->mac_type) {
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+ case e1000_82571:
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+ case e1000_82572:
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+ if (hw->leave_av_bit_off == TRUE)
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+ break;
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+ default:
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+ /* Indicate to hardware the Address is Valid. */
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+ rar_high |= E1000_RAH_AV;
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+ break;
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+ }
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E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
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E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
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