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@@ -403,7 +403,7 @@ static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
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/* used only at init
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* locking is done by mcp
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*/
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-void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
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+static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
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{
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pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
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pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
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@@ -429,7 +429,8 @@ static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
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#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
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#define DMAE_DP_DST_NONE "dst_addr [none]"
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-void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl)
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+static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
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+ int msglvl)
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{
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u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
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@@ -551,8 +552,9 @@ u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
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return opcode;
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}
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-void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
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- u8 src_type, u8 dst_type)
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+static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
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+ struct dmae_command *dmae,
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+ u8 src_type, u8 dst_type)
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{
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memset(dmae, 0, sizeof(struct dmae_command));
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@@ -567,7 +569,8 @@ void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
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}
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/* issue a dmae command over the init-channel and wailt for completion */
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-int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
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+static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
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+ struct dmae_command *dmae)
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{
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u32 *wb_comp = bnx2x_sp(bp, wb_comp);
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int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 40;
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@@ -674,8 +677,8 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
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bnx2x_issue_dmae_with_comp(bp, &dmae);
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}
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-void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
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- u32 addr, u32 len)
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+static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
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+ u32 addr, u32 len)
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{
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int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
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int offset = 0;
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@@ -1267,7 +1270,7 @@ static void bnx2x_igu_int_disable(struct bnx2x *bp)
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BNX2X_ERR("BUG! proper val not read from IGU!\n");
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}
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-void bnx2x_int_disable(struct bnx2x *bp)
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+static void bnx2x_int_disable(struct bnx2x *bp)
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{
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if (bp->common.int_block == INT_BLOCK_HC)
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bnx2x_hc_int_disable(bp);
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@@ -2236,7 +2239,7 @@ u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
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}
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/* must be called under rtnl_lock */
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-void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
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+static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
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{
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u32 mask = (1 << cl_id);
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@@ -2303,7 +2306,7 @@ void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
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bp->mac_filters.unmatched_unicast & ~mask;
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}
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-void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
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+static void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
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{
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struct tstorm_eth_function_common_config tcfg = {0};
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u16 rss_flgs;
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@@ -2460,7 +2463,7 @@ static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
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txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
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}
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-void bnx2x_pf_init(struct bnx2x *bp)
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+static void bnx2x_pf_init(struct bnx2x *bp)
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{
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struct bnx2x_func_init_params func_init = {0};
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struct bnx2x_rss_params rss = {0};
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@@ -3928,7 +3931,7 @@ void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
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hc_sm->time_to_expire = 0xFFFFFFFF;
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}
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-void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
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+static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
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u8 vf_valid, int fw_sb_id, int igu_sb_id)
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{
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int igu_seg_id;
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@@ -6021,6 +6024,9 @@ alloc_mem_err:
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/*
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* Init service functions
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*/
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+static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
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+ int *state_p, int flags);
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+
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int bnx2x_func_start(struct bnx2x *bp)
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{
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bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 0, 0, 1);
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@@ -6030,7 +6036,7 @@ int bnx2x_func_start(struct bnx2x *bp)
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WAIT_RAMROD_COMMON);
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}
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-int bnx2x_func_stop(struct bnx2x *bp)
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+static int bnx2x_func_stop(struct bnx2x *bp)
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{
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bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 1);
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@@ -6103,8 +6109,8 @@ static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, u8 *mac,
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bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, ramrod_flags);
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}
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-int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
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- int *state_p, int flags)
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+static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
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+ int *state_p, int flags)
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{
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/* can take a while if any port is running */
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int cnt = 5000;
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@@ -6154,7 +6160,7 @@ int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
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return -EBUSY;
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}
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-u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
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+static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
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{
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if (CHIP_IS_E1H(bp))
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return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);
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@@ -6273,7 +6279,7 @@ static void bnx2x_invlidate_e1_mc_list(struct bnx2x *bp)
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*
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* @return 0 if cussess, -ENODEV if ramrod doesn't return.
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*/
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-int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
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+static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
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{
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u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
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bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
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@@ -6383,11 +6389,11 @@ static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
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ETH_CONNECTION_TYPE);
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}
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-int bnx2x_setup_fw_client(struct bnx2x *bp,
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- struct bnx2x_client_init_params *params,
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- u8 activate,
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- struct client_init_ramrod_data *data,
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- dma_addr_t data_mapping)
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+static int bnx2x_setup_fw_client(struct bnx2x *bp,
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+ struct bnx2x_client_init_params *params,
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+ u8 activate,
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+ struct client_init_ramrod_data *data,
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+ dma_addr_t data_mapping)
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{
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u16 hc_usec;
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int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
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@@ -6633,7 +6639,8 @@ int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
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return rc;
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}
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-int bnx2x_stop_fw_client(struct bnx2x *bp, struct bnx2x_client_ramrod_params *p)
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+static int bnx2x_stop_fw_client(struct bnx2x *bp,
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+ struct bnx2x_client_ramrod_params *p)
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{
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int rc;
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@@ -7440,7 +7447,7 @@ reset_task_exit:
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* Init service functions
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*/
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-u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
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+static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
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{
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u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
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u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
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