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@@ -11,7 +11,9 @@ have PPIs or SGIs.
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Main node required properties:
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- compatible : should be one of:
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+ "arm,cortex-a15-gic"
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"arm,cortex-a9-gic"
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+ "arm,cortex-a7-gic"
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"arm,arm11mp-gic"
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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@@ -39,8 +41,9 @@ Main node required properties:
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the GIC cpu interface register base and size.
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Optional
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-- interrupts : Interrupt source of the parent interrupt controller. Only
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- present on secondary GICs.
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+- interrupts : Interrupt source of the parent interrupt controller on
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+ secondary GICs, or VGIC maintainance interrupt on primary GIC (see
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+ below).
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- cpu-offset : per-cpu offset within the distributor and cpu interface
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regions, used when the GIC doesn't have banked registers. The offset is
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@@ -57,3 +60,31 @@ Example:
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<0xfff10100 0x100>;
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};
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+
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+* GIC virtualization extensions (VGIC)
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+
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+For ARM cores that support the virtualization extensions, additional
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+properties must be described (they only exist if the GIC is the
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+primary interrupt controller).
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+
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+Required properties:
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+
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+- reg : Additional regions specifying the base physical address and
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+ size of the VGIC registers. The first additional region is the GIC
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+ virtual interface control register base and size. The 2nd additional
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+ region is the GIC virtual cpu interface register base and size.
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+
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+- interrupts : VGIC maintainance interrupt.
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+
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+Example:
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+
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+ interrupt-controller@2c001000 {
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+ compatible = "arm,cortex-a15-gic";
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+ #interrupt-cells = <3>;
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+ interrupt-controller;
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+ reg = <0x2c001000 0x1000>,
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+ <0x2c002000 0x1000>,
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+ <0x2c004000 0x2000>,
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+ <0x2c006000 0x2000>;
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+ interrupts = <1 9 0xf04>;
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+ };
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