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@@ -301,6 +301,26 @@ static const struct ipath_cregs ipath_pe_cregs = {
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*/
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*/
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#define INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR (1ULL<<63)
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#define INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR (1ULL<<63)
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+/* 6120 specific hardware errors... */
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+static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
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+ INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
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+ INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
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+ /*
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+ * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
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+ * parity or memory parity error failures, because most likely we
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+ * won't be able to talk to the core of the chip. Nonetheless, we
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+ * might see them, if they are in parts of the PCIe core that aren't
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+ * essential.
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+ */
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+ INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
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+ INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
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+ INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
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+ INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
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+ INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
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+ INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
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+ INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
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+};
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+
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/**
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/**
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* ipath_pe_handle_hwerrors - display hardware errors.
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* ipath_pe_handle_hwerrors - display hardware errors.
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* @dd: the infinipath device
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* @dd: the infinipath device
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@@ -403,24 +423,13 @@ static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
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ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
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ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
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dd->ipath_hwerrmask);
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dd->ipath_hwerrmask);
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}
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}
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- if (hwerrs & (INFINIPATH_HWE_RXEMEMPARITYERR_MASK
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- << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)) {
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- bits = (u32) ((hwerrs >>
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- INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) &
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- INFINIPATH_HWE_RXEMEMPARITYERR_MASK);
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- snprintf(bitsmsg, sizeof bitsmsg, "[RXE Parity Errs %x] ",
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- bits);
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- strlcat(msg, bitsmsg, msgl);
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- }
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- if (hwerrs & (INFINIPATH_HWE_TXEMEMPARITYERR_MASK
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- << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
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- bits = (u32) ((hwerrs >>
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- INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) &
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- INFINIPATH_HWE_TXEMEMPARITYERR_MASK);
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- snprintf(bitsmsg, sizeof bitsmsg, "[TXE Parity Errs %x] ",
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- bits);
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- strlcat(msg, bitsmsg, msgl);
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- }
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+
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+ ipath_format_hwerrors(hwerrs,
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+ ipath_6120_hwerror_msgs,
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+ sizeof(ipath_6120_hwerror_msgs)/
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+ sizeof(ipath_6120_hwerror_msgs[0]),
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+ msg, msgl);
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+
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if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
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if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
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<< INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
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<< INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
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bits = (u32) ((hwerrs >>
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bits = (u32) ((hwerrs >>
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@@ -430,10 +439,6 @@ static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
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"[PCIe Mem Parity Errs %x] ", bits);
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"[PCIe Mem Parity Errs %x] ", bits);
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strlcat(msg, bitsmsg, msgl);
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strlcat(msg, bitsmsg, msgl);
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}
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}
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- if (hwerrs & INFINIPATH_HWE_IBCBUSTOSPCPARITYERR)
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- strlcat(msg, "[IB2IPATH Parity]", msgl);
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- if (hwerrs & INFINIPATH_HWE_IBCBUSFRSPCPARITYERR)
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- strlcat(msg, "[IPATH2IB Parity]", msgl);
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#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
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#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
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INFINIPATH_HWE_COREPLL_RFSLIP )
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INFINIPATH_HWE_COREPLL_RFSLIP )
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@@ -459,34 +464,6 @@ static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
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dd->ipath_hwerrmask);
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dd->ipath_hwerrmask);
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}
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}
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- if (hwerrs & INFINIPATH_HWE_PCIEPOISONEDTLP)
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- strlcat(msg, "[PCIe Poisoned TLP]", msgl);
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- if (hwerrs & INFINIPATH_HWE_PCIECPLTIMEOUT)
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- strlcat(msg, "[PCIe completion timeout]", msgl);
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-
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- /*
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- * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
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- * parity or memory parity error failures, because most likely we
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- * won't be able to talk to the core of the chip. Nonetheless, we
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- * might see them, if they are in parts of the PCIe core that aren't
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- * essential.
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- */
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- if (hwerrs & INFINIPATH_HWE_PCIE1PLLFAILED)
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- strlcat(msg, "[PCIePLL1]", msgl);
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- if (hwerrs & INFINIPATH_HWE_PCIE0PLLFAILED)
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- strlcat(msg, "[PCIePLL0]", msgl);
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- if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYXTLH)
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- strlcat(msg, "[PCIe XTLH core parity]", msgl);
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- if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYXADM)
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- strlcat(msg, "[PCIe ADM TX core parity]", msgl);
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- if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYRADM)
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- strlcat(msg, "[PCIe ADM RX core parity]", msgl);
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-
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- if (hwerrs & INFINIPATH_HWE_RXDSYNCMEMPARITYERR)
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- strlcat(msg, "[Rx Dsync]", msgl);
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- if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED)
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- strlcat(msg, "[SerDes PLL]", msgl);
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-
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ipath_dev_err(dd, "%s hardware error\n", msg);
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ipath_dev_err(dd, "%s hardware error\n", msg);
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if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
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if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
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/*
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/*
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