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@@ -74,8 +74,8 @@
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#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
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#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
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#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
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#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
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#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
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#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
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-/* 14 free */
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-/* 15 free */
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+#define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */
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+#define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */
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#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
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#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
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#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
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#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
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#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
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#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
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