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@@ -35,6 +35,8 @@
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i-cache-line-size = <32>;
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d-cache-size = <32768>; // L1
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i-cache-size = <32768>; // L1
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+ sleep = <&pmc 0x00008000 0 // core
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+ &pmc 0x00004000 0>; // timebase
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timebase-frequency = <0>; // From uboot
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bus-frequency = <0>; // From uboot
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clock-frequency = <0>; // From uboot
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@@ -60,6 +62,7 @@
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5 0 0xe8480000 0x00008000
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6 0 0xe84c0000 0x00008000
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3 0 0xe8000000 0x00000020>;
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+ sleep = <&pmc 0x08000000 0>;
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flash@0,0 {
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compatible = "cfi-flash";
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@@ -105,6 +108,8 @@
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compatible = "fsl,fpga-pixis";
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reg = <3 0 0x20>;
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ranges = <0 3 0 0x20>;
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+ interrupt-parent = <&mpic>;
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+ interrupts = <8 8>;
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sdcsr_pio: gpio-controller@a {
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#gpio-cells = <2>;
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@@ -163,6 +168,7 @@
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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+ sleep = <&pmc 0x00000004 0>;
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dfsrr;
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};
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@@ -174,6 +180,7 @@
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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+ sleep = <&pmc 0x00000002 0>;
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};
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serial1: serial@4600 {
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@@ -184,6 +191,7 @@
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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+ sleep = <&pmc 0x00000008 0>;
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};
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spi@7000 {
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@@ -196,6 +204,7 @@
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interrupt-parent = <&mpic>;
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mode = "cpu";
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gpios = <&sdcsr_pio 7 0>;
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+ sleep = <&pmc 0x00000800 0>;
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mmc-slot@0 {
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compatible = "fsl,mpc8610hpcd-mmc-slot",
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@@ -213,6 +222,7 @@
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reg = <0x2c000 100>;
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interrupts = <72 2>;
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interrupt-parent = <&mpic>;
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+ sleep = <&pmc 0x04000000 0>;
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};
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mpic: interrupt-controller@40000 {
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@@ -241,9 +251,18 @@
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};
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global-utilities@e0000 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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compatible = "fsl,mpc8610-guts";
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reg = <0xe0000 0x1000>;
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+ ranges = <0 0xe0000 0x1000>;
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fsl,has-rstcr;
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+
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+ pmc: power@70 {
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+ compatible = "fsl,mpc8610-pmc",
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+ "fsl,mpc8641d-pmc";
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+ reg = <0x70 0x20>;
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+ };
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};
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wdt@e4000 {
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@@ -262,6 +281,7 @@
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fsl,playback-dma = <&dma00>;
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fsl,capture-dma = <&dma01>;
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fsl,fifo-depth = <8>;
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+ sleep = <&pmc 0 0x08000000>;
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};
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ssi@16100 {
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@@ -271,6 +291,7 @@
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interrupt-parent = <&mpic>;
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interrupts = <63 2>;
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fsl,fifo-depth = <8>;
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+ sleep = <&pmc 0 0x04000000>;
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};
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dma@21300 {
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@@ -280,6 +301,7 @@
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cell-index = <0>;
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reg = <0x21300 0x4>; /* DMA general status register */
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ranges = <0x0 0x21100 0x200>;
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+ sleep = <&pmc 0x00000400 0>;
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dma00: dma-channel@0 {
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compatible = "fsl,mpc8610-dma-channel",
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@@ -322,6 +344,7 @@
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cell-index = <1>;
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reg = <0xc300 0x4>; /* DMA general status register */
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ranges = <0x0 0xc100 0x200>;
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+ sleep = <&pmc 0x00000200 0>;
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dma-channel@0 {
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compatible = "fsl,mpc8610-dma-channel",
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@@ -369,6 +392,7 @@
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bus-range = <0 0>;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
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+ sleep = <&pmc 0x80000000 0>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <24 2>;
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@@ -398,6 +422,7 @@
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bus-range = <1 3>;
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ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
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+ sleep = <&pmc 0x40000000 0>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <26 2>;
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@@ -474,6 +499,7 @@
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0x0000 0 0 4 &mpic 7 1>;
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interrupt-parent = <&mpic>;
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interrupts = <25 2>;
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+ sleep = <&pmc 0x20000000 0>;
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clock-frequency = <33333333>;
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};
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};
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