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@@ -667,9 +667,8 @@ static int kv_program_bootup_state(struct radeon_device *rdev)
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&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
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if (table && table->count) {
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- for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
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- if ((table->entries[i].clk == pi->boot_pl.sclk) ||
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- (i == 0))
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+ for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
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+ if (table->entries[i].clk == pi->boot_pl.sclk)
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break;
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}
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@@ -682,9 +681,8 @@ static int kv_program_bootup_state(struct radeon_device *rdev)
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if (table->num_max_dpm_entries == 0)
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return -EINVAL;
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- for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
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- if ((table->entries[i].sclk_frequency == pi->boot_pl.sclk) ||
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- (i == 0))
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+ for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
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+ if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
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break;
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}
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@@ -1588,13 +1586,11 @@ static void kv_set_valid_clock_range(struct radeon_device *rdev,
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}
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}
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- for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
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- if ((table->entries[i].clk <= new_ps->levels[new_ps->num_levels -1].sclk) ||
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- (i == 0)) {
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- pi->highest_valid = i;
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+ for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
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+ if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
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break;
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- }
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}
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+ pi->highest_valid = i;
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if (pi->lowest_valid > pi->highest_valid) {
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if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
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@@ -1615,14 +1611,12 @@ static void kv_set_valid_clock_range(struct radeon_device *rdev,
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}
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}
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- for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
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+ for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
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if (table->entries[i].sclk_frequency <=
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- new_ps->levels[new_ps->num_levels - 1].sclk ||
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- i == 0) {
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- pi->highest_valid = i;
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+ new_ps->levels[new_ps->num_levels - 1].sclk)
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break;
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- }
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}
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+ pi->highest_valid = i;
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if (pi->lowest_valid > pi->highest_valid) {
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if ((new_ps->levels[0].sclk -
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@@ -1871,7 +1865,7 @@ static int kv_force_dpm_highest(struct radeon_device *rdev)
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if (ret)
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return ret;
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- for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i >= 0; i--) {
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+ for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
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if (enable_mask & (1 << i))
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break;
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}
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@@ -1911,9 +1905,9 @@ static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
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if (!pi->caps_sclk_ds)
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return 0;
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- for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i <= 0; i--) {
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+ for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
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temp = sclk / sumo_get_sleep_divider_from_id(i);
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- if ((temp >= min) || (i == 0))
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+ if (temp >= min)
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break;
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}
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