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@@ -30,6 +30,14 @@
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#define MAILBOX_IRQ_NEWMSG(u) (1 << (2 * (u)))
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#define MAILBOX_IRQ_NEWMSG(u) (1 << (2 * (u)))
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#define MAILBOX_IRQ_NOTFULL(u) (1 << (2 * (u) + 1))
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#define MAILBOX_IRQ_NOTFULL(u) (1 << (2 * (u) + 1))
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+/* SYSCONFIG: register bit definition */
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+#define AUTOIDLE (1 << 0)
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+#define SOFTRESET (1 << 1)
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+#define SMARTIDLE (2 << 3)
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+
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+/* SYSSTATUS: register bit definition */
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+#define RESETDONE (1 << 0)
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+
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#define MBOX_REG_SIZE 0x120
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#define MBOX_REG_SIZE 0x120
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#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
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#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
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@@ -69,21 +77,33 @@ static inline void mbox_write_reg(u32 val, size_t ofs)
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/* Mailbox H/W preparations */
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/* Mailbox H/W preparations */
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static int omap2_mbox_startup(struct omap_mbox *mbox)
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static int omap2_mbox_startup(struct omap_mbox *mbox)
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{
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{
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- unsigned int l;
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+ u32 l;
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+ unsigned long timeout;
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mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
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mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
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if (IS_ERR(mbox_ick_handle)) {
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if (IS_ERR(mbox_ick_handle)) {
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- printk("Could not get mailboxes_ick\n");
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+ pr_err("Can't get mailboxes_ick\n");
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return -ENODEV;
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return -ENODEV;
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}
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}
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clk_enable(mbox_ick_handle);
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clk_enable(mbox_ick_handle);
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+ mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
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+ timeout = jiffies + msecs_to_jiffies(20);
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+ do {
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+ l = mbox_read_reg(MAILBOX_SYSSTATUS);
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+ if (l & RESETDONE)
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+ break;
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+ } while (!time_after(jiffies, timeout));
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+
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+ if (!(l & RESETDONE)) {
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+ pr_err("Can't take mmu out of reset\n");
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+ return -ENODEV;
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+ }
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+
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l = mbox_read_reg(MAILBOX_REVISION);
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l = mbox_read_reg(MAILBOX_REVISION);
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pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
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pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
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- /* set smart-idle & autoidle */
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- l = mbox_read_reg(MAILBOX_SYSCONFIG);
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- l |= 0x00000011;
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+ l = SMARTIDLE | AUTOIDLE;
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mbox_write_reg(l, MAILBOX_SYSCONFIG);
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mbox_write_reg(l, MAILBOX_SYSCONFIG);
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omap2_mbox_enable_irq(mbox, IRQ_RX);
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omap2_mbox_enable_irq(mbox, IRQ_RX);
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@@ -156,6 +176,9 @@ static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
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u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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mbox_write_reg(bit, p->irqstatus);
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mbox_write_reg(bit, p->irqstatus);
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+
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+ /* Flush posted write for irq status to avoid spurious interrupts */
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+ mbox_read_reg(p->irqstatus);
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}
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}
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static int omap2_mbox_is_irq(struct omap_mbox *mbox,
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static int omap2_mbox_is_irq(struct omap_mbox *mbox,
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