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+/*
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+ * linux/arch/arm/mach-omap2/sleep.S
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+ *
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+ * (C) Copyright 2007
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+ * Texas Instruments
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+ * Karthik Dasu <karthik-dp@ti.com>
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+ *
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+ * (C) Copyright 2004
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+ * Texas Instruments, <www.ti.com>
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+ * Richard Woodruff <r-woodruff2@ti.com>
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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+ * MA 02111-1307 USA
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+ */
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+#include <linux/linkage.h>
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+#include <asm/assembler.h>
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+#include <mach/io.h>
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+#include <mach/control.h>
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+
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+#include "prm.h"
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+#include "sdrc.h"
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+
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+#define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \
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+ OMAP3430_PM_PREPWSTST)
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+#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
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+ OMAP3430_PM_PREPWSTST)
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+#define PM_PWSTCTRL_MPU_P OMAP34XX_PRM_REGADDR(MPU_MOD, PM_PWSTCTRL)
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+#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
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+ * available */
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+#define SCRATCHPAD_BASE_P OMAP343X_CTRL_REGADDR(\
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+ OMAP343X_CONTROL_MEM_WKUP +\
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+ SCRATCHPAD_MEM_OFFS)
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+#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
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+
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+ .text
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+/* Function call to get the restore pointer for resume from OFF */
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+ENTRY(get_restore_pointer)
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+ stmfd sp!, {lr} @ save registers on stack
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+ adr r0, restore
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+ ldmfd sp!, {pc} @ restore regs and return
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+ENTRY(get_restore_pointer_sz)
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+ .word . - get_restore_pointer_sz
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+/*
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+ * Forces OMAP into idle state
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+ *
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+ * omap34xx_suspend() - This bit of code just executes the WFI
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+ * for normal idles.
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+ *
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+ * Note: This code get's copied to internal SRAM at boot. When the OMAP
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+ * wakes up it continues execution at the point it went to sleep.
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+ */
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+ENTRY(omap34xx_cpu_suspend)
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+ stmfd sp!, {r0-r12, lr} @ save registers on stack
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+loop:
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+ /*b loop*/ @Enable to debug by stepping through code
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+ /* r0 contains restore pointer in sdram */
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+ /* r1 contains information about saving context */
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+ ldr r4, sdrc_power @ read the SDRC_POWER register
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+ ldr r5, [r4] @ read the contents of SDRC_POWER
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+ orr r5, r5, #0x40 @ enable self refresh on idle req
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+ str r5, [r4] @ write back to SDRC_POWER register
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+
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+ cmp r1, #0x0
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+ /* If context save is required, do that and execute wfi */
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+ bne save_context_wfi
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+ /* Data memory barrier and Data sync barrier */
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+ mov r1, #0
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+ mcr p15, 0, r1, c7, c10, 4
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+ mcr p15, 0, r1, c7, c10, 5
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+
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+ wfi @ wait for interrupt
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+
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+ nop
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+ nop
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+ nop
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+ nop
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+ nop
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+ nop
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+ nop
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+ nop
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+ nop
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+ nop
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+ bl i_dll_wait
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+
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+ ldmfd sp!, {r0-r12, pc} @ restore regs and return
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+restore:
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+ /* b restore*/ @ Enable to debug restore code
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+ /* Check what was the reason for mpu reset and store the reason in r9*/
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+ /* 1 - Only L1 and logic lost */
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+ /* 2 - Only L2 lost - In this case, we wont be here */
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+ /* 3 - Both L1 and L2 lost */
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+ ldr r1, pm_pwstctrl_mpu
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+ ldr r2, [r1]
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+ and r2, r2, #0x3
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+ cmp r2, #0x0 @ Check if target power state was OFF or RET
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+ moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
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+ movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation
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+ bne logic_l1_restore
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+ /* Execute smi to invalidate L2 cache */
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+ mov r12, #0x1 @ set up to invalide L2
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+smi: .word 0xE1600070 @ Call SMI monitor (smieq)
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+logic_l1_restore:
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+ mov r1, #0
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+ /* Invalidate all instruction caches to PoU
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+ * and flush branch target cache */
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+ mcr p15, 0, r1, c7, c5, 0
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+
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+ ldr r4, scratchpad_base
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+ ldr r3, [r4,#0xBC]
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+ ldmia r3!, {r4-r6}
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+ mov sp, r4
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+ msr spsr_cxsf, r5
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+ mov lr, r6
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+
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+ ldmia r3!, {r4-r9}
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+ /* Coprocessor access Control Register */
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+ mcr p15, 0, r4, c1, c0, 2
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+
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+ /* TTBR0 */
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+ MCR p15, 0, r5, c2, c0, 0
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+ /* TTBR1 */
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+ MCR p15, 0, r6, c2, c0, 1
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+ /* Translation table base control register */
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+ MCR p15, 0, r7, c2, c0, 2
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+ /*domain access Control Register */
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+ MCR p15, 0, r8, c3, c0, 0
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+ /* data fault status Register */
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+ MCR p15, 0, r9, c5, c0, 0
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+
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+ ldmia r3!,{r4-r8}
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+ /* instruction fault status Register */
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+ MCR p15, 0, r4, c5, c0, 1
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+ /*Data Auxiliary Fault Status Register */
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+ MCR p15, 0, r5, c5, c1, 0
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+ /*Instruction Auxiliary Fault Status Register*/
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+ MCR p15, 0, r6, c5, c1, 1
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+ /*Data Fault Address Register */
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+ MCR p15, 0, r7, c6, c0, 0
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+ /*Instruction Fault Address Register*/
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+ MCR p15, 0, r8, c6, c0, 2
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+ ldmia r3!,{r4-r7}
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+
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+ /* user r/w thread and process ID */
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+ MCR p15, 0, r4, c13, c0, 2
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+ /* user ro thread and process ID */
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+ MCR p15, 0, r5, c13, c0, 3
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+ /*Privileged only thread and process ID */
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+ MCR p15, 0, r6, c13, c0, 4
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+ /* cache size selection */
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+ MCR p15, 2, r7, c0, c0, 0
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+ ldmia r3!,{r4-r8}
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+ /* Data TLB lockdown registers */
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+ MCR p15, 0, r4, c10, c0, 0
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+ /* Instruction TLB lockdown registers */
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+ MCR p15, 0, r5, c10, c0, 1
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+ /* Secure or Nonsecure Vector Base Address */
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+ MCR p15, 0, r6, c12, c0, 0
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+ /* FCSE PID */
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+ MCR p15, 0, r7, c13, c0, 0
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+ /* Context PID */
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+ MCR p15, 0, r8, c13, c0, 1
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+
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+ ldmia r3!,{r4-r5}
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+ /* primary memory remap register */
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+ MCR p15, 0, r4, c10, c2, 0
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+ /*normal memory remap register */
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+ MCR p15, 0, r5, c10, c2, 1
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+
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+ /* Restore cpsr */
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+ ldmia r3!,{r4} /*load CPSR from SDRAM*/
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+ msr cpsr, r4 /*store cpsr */
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+
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+ /* Enabling MMU here */
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+ mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */
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+ /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/
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+ and r7, #0x7
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+ cmp r7, #0x0
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+ beq usettbr0
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+ttbr_error:
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+ /* More work needs to be done to support N[0:2] value other than 0
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+ * So looping here so that the error can be detected
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+ */
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+ b ttbr_error
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+usettbr0:
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+ mrc p15, 0, r2, c2, c0, 0
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+ ldr r5, ttbrbit_mask
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+ and r2, r5
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+ mov r4, pc
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+ ldr r5, table_index_mask
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+ and r4, r5 /* r4 = 31 to 20 bits of pc */
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+ /* Extract the value to be written to table entry */
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+ ldr r1, table_entry
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+ add r1, r1, r4 /* r1 has value to be written to table entry*/
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+ /* Getting the address of table entry to modify */
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+ lsr r4, #18
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+ add r2, r4 /* r2 has the location which needs to be modified */
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+ /* Storing previous entry of location being modified */
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+ ldr r5, scratchpad_base
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+ ldr r4, [r2]
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+ str r4, [r5, #0xC0]
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+ /* Modify the table entry */
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+ str r1, [r2]
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+ /* Storing address of entry being modified
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+ * - will be restored after enabling MMU */
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+ ldr r5, scratchpad_base
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+ str r2, [r5, #0xC4]
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+
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+ mov r0, #0
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+ mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
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+ mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
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+ mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
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+ mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
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+ /* Restore control register but dont enable caches here*/
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+ /* Caches will be enabled after restoring MMU table entry */
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+ ldmia r3!, {r4}
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+ /* Store previous value of control register in scratchpad */
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+ str r4, [r5, #0xC8]
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+ ldr r2, cache_pred_disable_mask
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+ and r4, r2
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+ mcr p15, 0, r4, c1, c0, 0
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+
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+ ldmfd sp!, {r0-r12, pc} @ restore regs and return
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+save_context_wfi:
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+ /*b save_context_wfi*/ @ enable to debug save code
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+ mov r8, r0 /* Store SDRAM address in r8 */
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+ /* Check what that target sleep state is:stored in r1*/
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+ /* 1 - Only L1 and logic lost */
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+ /* 2 - Only L2 lost */
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+ /* 3 - Both L1 and L2 lost */
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+ cmp r1, #0x2 /* Only L2 lost */
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+ beq clean_l2
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+ cmp r1, #0x1 /* L2 retained */
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+ /* r9 stores whether to clean L2 or not*/
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+ moveq r9, #0x0 /* Dont Clean L2 */
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+ movne r9, #0x1 /* Clean L2 */
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+l1_logic_lost:
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+ /* Store sp and spsr to SDRAM */
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+ mov r4, sp
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+ mrs r5, spsr
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+ mov r6, lr
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+ stmia r8!, {r4-r6}
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+ /* Save all ARM registers */
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+ /* Coprocessor access control register */
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+ mrc p15, 0, r6, c1, c0, 2
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+ stmia r8!, {r6}
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+ /* TTBR0, TTBR1 and Translation table base control */
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+ mrc p15, 0, r4, c2, c0, 0
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+ mrc p15, 0, r5, c2, c0, 1
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+ mrc p15, 0, r6, c2, c0, 2
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+ stmia r8!, {r4-r6}
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+ /* Domain access control register, data fault status register,
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+ and instruction fault status register */
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+ mrc p15, 0, r4, c3, c0, 0
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+ mrc p15, 0, r5, c5, c0, 0
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+ mrc p15, 0, r6, c5, c0, 1
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+ stmia r8!, {r4-r6}
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+ /* Data aux fault status register, instruction aux fault status,
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+ datat fault address register and instruction fault address register*/
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+ mrc p15, 0, r4, c5, c1, 0
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+ mrc p15, 0, r5, c5, c1, 1
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+ mrc p15, 0, r6, c6, c0, 0
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+ mrc p15, 0, r7, c6, c0, 2
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+ stmia r8!, {r4-r7}
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+ /* user r/w thread and process ID, user r/o thread and process ID,
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+ priv only thread and process ID, cache size selection */
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+ mrc p15, 0, r4, c13, c0, 2
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+ mrc p15, 0, r5, c13, c0, 3
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+ mrc p15, 0, r6, c13, c0, 4
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+ mrc p15, 2, r7, c0, c0, 0
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+ stmia r8!, {r4-r7}
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+ /* Data TLB lockdown, instruction TLB lockdown registers */
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+ mrc p15, 0, r5, c10, c0, 0
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+ mrc p15, 0, r6, c10, c0, 1
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+ stmia r8!, {r5-r6}
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+ /* Secure or non secure vector base address, FCSE PID, Context PID*/
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+ mrc p15, 0, r4, c12, c0, 0
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+ mrc p15, 0, r5, c13, c0, 0
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+ mrc p15, 0, r6, c13, c0, 1
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+ stmia r8!, {r4-r6}
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+ /* Primary remap, normal remap registers */
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+ mrc p15, 0, r4, c10, c2, 0
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+ mrc p15, 0, r5, c10, c2, 1
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+ stmia r8!,{r4-r5}
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+
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+ /* Store current cpsr*/
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+ mrs r2, cpsr
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+ stmia r8!, {r2}
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+
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+ mrc p15, 0, r4, c1, c0, 0
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+ /* save control register */
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+ stmia r8!, {r4}
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+clean_caches:
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+ /* Clean Data or unified cache to POU*/
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+ /* How to invalidate only L1 cache???? - #FIX_ME# */
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+ /* mcr p15, 0, r11, c7, c11, 1 */
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+ cmp r9, #1 /* Check whether L2 inval is required or not*/
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+ bne skip_l2_inval
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+clean_l2:
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+ /* read clidr */
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+ mrc p15, 1, r0, c0, c0, 1
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+ /* extract loc from clidr */
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+ ands r3, r0, #0x7000000
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+ /* left align loc bit field */
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+ mov r3, r3, lsr #23
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+ /* if loc is 0, then no need to clean */
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+ beq finished
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+ /* start clean at cache level 0 */
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+ mov r10, #0
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+loop1:
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+ /* work out 3x current cache level */
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+ add r2, r10, r10, lsr #1
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+ /* extract cache type bits from clidr*/
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+ mov r1, r0, lsr r2
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+ /* mask of the bits for current cache only */
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+ and r1, r1, #7
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+ /* see what cache we have at this level */
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+ cmp r1, #2
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+ /* skip if no cache, or just i-cache */
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+ blt skip
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+ /* select current cache level in cssr */
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+ mcr p15, 2, r10, c0, c0, 0
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+ /* isb to sych the new cssr&csidr */
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+ isb
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+ /* read the new csidr */
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+ mrc p15, 1, r1, c0, c0, 0
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+ /* extract the length of the cache lines */
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+ and r2, r1, #7
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+ /* add 4 (line length offset) */
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+ add r2, r2, #4
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+ ldr r4, assoc_mask
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+ /* find maximum number on the way size */
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+ ands r4, r4, r1, lsr #3
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+ /* find bit position of way size increment */
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+ clz r5, r4
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+ ldr r7, numset_mask
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+ /* extract max number of the index size*/
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+ ands r7, r7, r1, lsr #13
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+loop2:
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+ mov r9, r4
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+ /* create working copy of max way size*/
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+loop3:
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+ /* factor way and cache number into r11 */
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+ orr r11, r10, r9, lsl r5
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+ /* factor index number into r11 */
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+ orr r11, r11, r7, lsl r2
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+ /*clean & invalidate by set/way */
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+ mcr p15, 0, r11, c7, c10, 2
|
|
|
+ /* decrement the way*/
|
|
|
+ subs r9, r9, #1
|
|
|
+ bge loop3
|
|
|
+ /*decrement the index */
|
|
|
+ subs r7, r7, #1
|
|
|
+ bge loop2
|
|
|
+skip:
|
|
|
+ add r10, r10, #2
|
|
|
+ /* increment cache number */
|
|
|
+ cmp r3, r10
|
|
|
+ bgt loop1
|
|
|
+finished:
|
|
|
+ /*swith back to cache level 0 */
|
|
|
+ mov r10, #0
|
|
|
+ /* select current cache level in cssr */
|
|
|
+ mcr p15, 2, r10, c0, c0, 0
|
|
|
+ isb
|
|
|
+skip_l2_inval:
|
|
|
+ /* Data memory barrier and Data sync barrier */
|
|
|
+ mov r1, #0
|
|
|
+ mcr p15, 0, r1, c7, c10, 4
|
|
|
+ mcr p15, 0, r1, c7, c10, 5
|
|
|
+
|
|
|
+ wfi @ wait for interrupt
|
|
|
+ nop
|
|
|
+ nop
|
|
|
+ nop
|
|
|
+ nop
|
|
|
+ nop
|
|
|
+ nop
|
|
|
+ nop
|
|
|
+ nop
|
|
|
+ nop
|
|
|
+ nop
|
|
|
+ bl i_dll_wait
|
|
|
+ /* restore regs and return */
|
|
|
+ ldmfd sp!, {r0-r12, pc}
|
|
|
+
|
|
|
+i_dll_wait:
|
|
|
+ ldr r4, clk_stabilize_delay
|
|
|
+
|
|
|
+i_dll_delay:
|
|
|
+ subs r4, r4, #0x1
|
|
|
+ bne i_dll_delay
|
|
|
+ ldr r4, sdrc_power
|
|
|
+ ldr r5, [r4]
|
|
|
+ bic r5, r5, #0x40
|
|
|
+ str r5, [r4]
|
|
|
+ bx lr
|
|
|
+pm_prepwstst_core:
|
|
|
+ .word PM_PREPWSTST_CORE_V
|
|
|
+pm_prepwstst_mpu:
|
|
|
+ .word PM_PREPWSTST_MPU_V
|
|
|
+pm_pwstctrl_mpu:
|
|
|
+ .word PM_PWSTCTRL_MPU_P
|
|
|
+scratchpad_base:
|
|
|
+ .word SCRATCHPAD_BASE_P
|
|
|
+sdrc_power:
|
|
|
+ .word SDRC_POWER_V
|
|
|
+context_mem:
|
|
|
+ .word 0x803E3E14
|
|
|
+clk_stabilize_delay:
|
|
|
+ .word 0x000001FF
|
|
|
+assoc_mask:
|
|
|
+ .word 0x3ff
|
|
|
+numset_mask:
|
|
|
+ .word 0x7fff
|
|
|
+ttbrbit_mask:
|
|
|
+ .word 0xFFFFC000
|
|
|
+table_index_mask:
|
|
|
+ .word 0xFFF00000
|
|
|
+table_entry:
|
|
|
+ .word 0x00000C02
|
|
|
+cache_pred_disable_mask:
|
|
|
+ .word 0xFFFFE7FB
|
|
|
+ENTRY(omap34xx_cpu_suspend_sz)
|
|
|
+ .word . - omap34xx_cpu_suspend
|