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@@ -52,8 +52,6 @@
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#define CSR_ONCE (1<<27)
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#define CSR_FLOW (1<<21)
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#define CSR_REQ_SEL_SHIFT 16
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-#define CSR_REQ_SEL_MASK (0x1F<<CSR_REQ_SEL_SHIFT)
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-#define CSR_REQ_SEL_INVALID (31<<CSR_REQ_SEL_SHIFT)
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#define CSR_WCOUNT_SHIFT 2
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#define CSR_WCOUNT_MASK 0xFFFC
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@@ -183,18 +181,12 @@ static void tegra_dma_stop(struct tegra_dma_channel *ch)
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static int tegra_dma_cancel(struct tegra_dma_channel *ch)
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{
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- u32 csr;
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unsigned long irq_flags;
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spin_lock_irqsave(&ch->lock, irq_flags);
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while (!list_empty(&ch->list))
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list_del(ch->list.next);
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- csr = readl(ch->addr + APB_DMA_CHAN_CSR);
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- csr &= ~CSR_REQ_SEL_MASK;
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- csr |= CSR_REQ_SEL_INVALID;
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- writel(csr, ch->addr + APB_DMA_CHAN_CSR);
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-
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tegra_dma_stop(ch);
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spin_unlock_irqrestore(&ch->lock, irq_flags);
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