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@@ -18,10 +18,26 @@
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#include <linux/module.h>
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#include <linux/string.h>
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#include <asm/hardware.h>
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-#include <asm/arch/ixp2000-regs.h>
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+#include <asm/arch/hardware.h>
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#include <asm/hardware/uengine.h>
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#include <asm/io.h>
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+#if defined(CONFIG_ARCH_IXP2000)
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+#define IXP_UENGINE_CSR_VIRT_BASE IXP2000_UENGINE_CSR_VIRT_BASE
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+#define IXP_PRODUCT_ID IXP2000_PRODUCT_ID
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+#define IXP_MISC_CONTROL IXP2000_MISC_CONTROL
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+#define IXP_RESET1 IXP2000_RESET1
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+#else
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+#if defined(CONFIG_ARCH_IXP23XX)
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+#define IXP_UENGINE_CSR_VIRT_BASE IXP23XX_UENGINE_CSR_VIRT_BASE
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+#define IXP_PRODUCT_ID IXP23XX_PRODUCT_ID
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+#define IXP_MISC_CONTROL IXP23XX_MISC_CONTROL
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+#define IXP_RESET1 IXP23XX_RESET1
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+#else
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+#error unknown platform
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+#endif
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+#endif
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+
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#define USTORE_ADDRESS 0x000
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#define USTORE_DATA_LOWER 0x004
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#define USTORE_DATA_UPPER 0x008
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@@ -43,7 +59,7 @@ u32 ixp2000_uengine_mask;
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static void *ixp2000_uengine_csr_area(int uengine)
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{
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- return ((void *)IXP2000_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
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+ return ((void *)IXP_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
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}
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/*
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@@ -91,8 +107,13 @@ EXPORT_SYMBOL(ixp2000_uengine_csr_write);
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void ixp2000_uengine_reset(u32 uengine_mask)
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{
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- ixp2000_reg_wrb(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask);
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- ixp2000_reg_wrb(IXP2000_RESET1, 0);
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+ u32 value;
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+
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+ value = ixp2000_reg_read(IXP_RESET1) & ~ixp2000_uengine_mask;
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+
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+ uengine_mask &= ixp2000_uengine_mask;
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+ ixp2000_reg_wrb(IXP_RESET1, value | uengine_mask);
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+ ixp2000_reg_wrb(IXP_RESET1, value);
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}
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EXPORT_SYMBOL(ixp2000_uengine_reset);
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@@ -235,11 +256,12 @@ static int check_ixp_type(struct ixp2000_uengine_code *c)
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u32 product_id;
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u32 rev;
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- product_id = ixp2000_reg_read(IXP2000_PRODUCT_ID);
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+ product_id = ixp2000_reg_read(IXP_PRODUCT_ID);
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if (((product_id >> 16) & 0x1f) != 0)
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return 0;
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switch ((product_id >> 8) & 0xff) {
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+#ifdef CONFIG_ARCH_IXP2000
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case 0: /* IXP2800 */
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if (!(c->cpu_model_bitmask & 4))
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return 0;
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@@ -254,6 +276,14 @@ static int check_ixp_type(struct ixp2000_uengine_code *c)
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if (!(c->cpu_model_bitmask & 2))
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return 0;
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break;
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+#endif
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+
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+#ifdef CONFIG_ARCH_IXP23XX
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+ case 4: /* IXP23xx */
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+ if (!(c->cpu_model_bitmask & 0x3f0))
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+ return 0;
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+ break;
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+#endif
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default:
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return 0;
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@@ -432,7 +462,8 @@ static int __init ixp2000_uengine_init(void)
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/*
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* Determine number of microengines present.
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*/
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- switch ((ixp2000_reg_read(IXP2000_PRODUCT_ID) >> 8) & 0x1fff) {
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+ switch ((ixp2000_reg_read(IXP_PRODUCT_ID) >> 8) & 0x1fff) {
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+#ifdef CONFIG_ARCH_IXP2000
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case 0: /* IXP2800 */
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case 1: /* IXP2850 */
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ixp2000_uengine_mask = 0x00ff00ff;
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@@ -441,10 +472,17 @@ static int __init ixp2000_uengine_init(void)
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case 2: /* IXP2400 */
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ixp2000_uengine_mask = 0x000f000f;
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break;
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+#endif
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+
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+#ifdef CONFIG_ARCH_IXP23XX
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+ case 4: /* IXP23xx */
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+ ixp2000_uengine_mask = (*IXP23XX_EXP_CFG_FUSE >> 8) & 0xf;
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+ break;
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+#endif
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default:
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printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n",
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- (unsigned int)ixp2000_reg_read(IXP2000_PRODUCT_ID));
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+ (unsigned int)ixp2000_reg_read(IXP_PRODUCT_ID));
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ixp2000_uengine_mask = 0x00000000;
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break;
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}
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@@ -457,15 +495,15 @@ static int __init ixp2000_uengine_init(void)
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/*
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* Synchronise timestamp counters across all microengines.
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*/
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- value = ixp2000_reg_read(IXP2000_MISC_CONTROL);
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- ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value & ~0x80);
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+ value = ixp2000_reg_read(IXP_MISC_CONTROL);
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+ ixp2000_reg_wrb(IXP_MISC_CONTROL, value & ~0x80);
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for (uengine = 0; uengine < 32; uengine++) {
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if (ixp2000_uengine_mask & (1 << uengine)) {
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ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
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ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
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}
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}
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- ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value | 0x80);
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+ ixp2000_reg_wrb(IXP_MISC_CONTROL, value | 0x80);
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return 0;
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}
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